公开(公告)号：US20220020865A1

公开(公告)日：2022-01-20

申请号：US17198133

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US20210398861A1

公开(公告)日：2021-12-23

申请号：US17018084

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/092

Abstract: A method includes depositing a first conductive layer over a gate dielectric layer; depositing a first work function tuning layer over the first conductive layer; selectively removing the first work function tuning layer from over a first region of the first conductive layer; doping the first work function tuning layer with a dopant; and after doping the first work function tuning layer performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function tuning layer. The first treatment process etches the first conductive layer at a greater rate than the first work function tuning layer.

公开(公告)号：US20210391331A1

公开(公告)日：2021-12-16

申请号：US16901885

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L27/108 ,  H01L29/423 ,  H01L49/02

Abstract: An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.

公开(公告)号：US20210376113A1

公开(公告)日：2021-12-02

申请号：US16952550

申请日：2020-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

公开(公告)号：US20210359096A1

公开(公告)日：2021-11-18

申请号：US16942310

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/28

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material over the first p-type work function metal; and a second p-type work function metal over the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal.

公开(公告)号：US20210313419A1

公开(公告)日：2021-10-07

申请号：US16842066

申请日：2020-04-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02

Abstract: A semiconductor device including a barrier layer surrounding a work function metal layer and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a second channel region over the first channel region; gate dielectric layers surrounding the first channel region and the second channel region; work function metal layers surrounding the gate dielectric layers; and barrier layers surrounding the work function metal layers, a first barrier layer surrounding the first channel region being merged with a second barrier layer surrounding the second channel region.

公开(公告)号：US20210242081A1

公开(公告)日：2021-08-05

申请号：US16884837

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Pin-Hsuan Yeh ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L21/768 ,  H01L29/423 ,  H01L29/78

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

公开(公告)号：US20210233817A1

公开(公告)日：2021-07-29

申请号：US16870485

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L21/8234 ,  C23C16/34 ,  C23C16/455 ,  H01L21/285 ,  H01L21/28 ,  H01L21/764 ,  H01L29/66 ,  H01L27/088 ,  H01L29/08 ,  H01L29/06 ,  H01L29/49 ,  H01L29/45 ,  H01L29/417

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. After the recessing, a portion of a semiconductor material between the isolation region protrudes higher than top surfaces of the isolation regions to form a semiconductor fin. The method further includes forming a gate stack, which includes forming a gate dielectric on sidewalls and a top surface of the semiconductor fin, and depositing a titanium nitride layer over the gate dielectric as a work-function layer. The titanium nitride layer is deposited at a temperature in a range between about 300° C. and about 400° C. A source region and a drain region are formed on opposing sides of the gate stack.

公开(公告)号：US20210193454A1

公开(公告)日：2021-06-24

申请号：US16943020

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/02 ,  C23C16/455

Abstract: A method includes placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate includes a trench, and performing an atomic layer deposition (ALD) process to deposit a dielectric material within the trench, including flowing a first precursor of the dielectric material into the deposition chamber as a gas phase; flowing a second precursor of the dielectric material into the deposition chamber as a gas phase; and controlling the pressure and temperature within the deposition chamber such that the second precursor condenses on surfaces within the trench as a liquid phase of the second precursor, wherein the liquid phase of the second precursor has capillarity.

公开(公告)号：US20210005727A1

公开(公告)日：2021-01-07

申请号：US17026976

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Ho Lin ,  Chun-Heng Chen ,  Xiong-Fei Yu ,  Chi On Chui

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A method includes forming a fin protruding over a substrate; forming a conformal oxide layer over an upper surface and along sidewalls of the fin; performing an anisotropic oxide deposition or an anisotropic plasma treatment to form a non-conformal oxide layer over the upper surface and along the sidewalls of the fin; and forming a gate electrode over the fin, the conformal oxide layer and the non-conformal oxide layer being between the fin and the gate electrode.