公开(公告)号：US20250149490A1

公开(公告)日：2025-05-08

申请号：US18830785

申请日：2024-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhee Lee ,  Yunrae Cho

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes a plurality of semiconductor chips stacked in a first direction, a plurality of chip connection terminals disposed between two semiconductor chips disposed adjacent to each other in the first direction among the plurality of semiconductor chips and electrically connecting the two adjacent semiconductor chips, and a plurality of chip support structures disposed between the two adjacent semiconductor chips. The plurality of chip support structures do not electrically connect the two adjacent semiconductor chips, and are spaced apart from the plurality of chip connection terminals in a second direction crossing the first direction. A thickness of each of the plurality of chip support structures is greater than a thickness of each of the plurality of chip connection terminals.

公开(公告)号：US20250149480A1

公开(公告)日：2025-05-08

申请号：US18804574

申请日：2024-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhee LEE ,  Yun-Rae CHO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes: a first semiconductor chip; and a second semiconductor chip connected to the first semiconductor chip, wherein the first semiconductor chip includes: a first semiconductor layer; a first through electrode penetrating the first semiconductor layer; and a first connection pad part positioned on the first semiconductor layer and including a plurality of first connection pads connected to the first through electrode, wherein the second semiconductor chip includes: a second semiconductor layer; a second through electrode penetrating the second semiconductor layer; and a second connection pad part positioned on the second semiconductor layer to face the first connection pad part and including a plurality of second connection pads connected to the second through electrode, wherein the plurality of first connection pads is in contact with the plurality of second connection pads, respectively.

公开(公告)号：US20250149479A1

公开(公告)日：2025-05-08

申请号：US18660617

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haksun LEE ,  Dohyun Kim ,  Yeongseon Kim ,  Juhyeon Kim ,  Hyoeun Kim ,  Sunkyoung Seo ,  Chajea Jo

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/10

Abstract: A semiconductor chip includes: a substrate; a plurality of upper pads on the substrate, the plurality of upper pads including a first group of the upper pads and a second group of the upper pads; a buffer layer covering a side surface of the first group of the upper pads; and an insulating layer surrounding a side surface of the second group of the upper pads and a side surface of the buffer layer on the substrate, wherein the buffer layer includes a first material having a first Young's modulus smaller than a second Young's modulus of a second material in the plurality of upper pads.

公开(公告)号：US20250149476A1

公开(公告)日：2025-05-08

申请号：US19014646

申请日：2025-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkyun KWON ,  Chulyong JANG

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. An active layer is disposed in a portion of the semiconductor substrate adjacent to the first surface. A through electrode extends in the semiconductor substrate in a vertical direction. The through electrode has a lower surface connected to the active layer and an upper surface positioned at a level lower than a level of the second surface of the semiconductor substrate. A passivation layer is disposed on the second surface of the semiconductor substrate. A bonding pad is arranged on a portion of the passivation layer and the upper surface of the through electrode. The bonding pad has a cross-section with a “T” shape in the vertical direction. The bonding pad is connected to the through electrode.

公开(公告)号：US20250149467A1

公开(公告)日：2025-05-08

申请号：US18917246

申请日：2024-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juil Choi ,  Jongho Park ,  Chanwook Park ,  Hyungjun Park ,  Taeoh Ha ,  Hongseo Heo

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a first die structure including a support substrate having a cavity, a first semiconductor chip in the cavity, and a first gap filling layer that fills a gap between an inner wall of the cavity and the first semiconductor chip; and a second die structure on the first die structure, the second die structure including a second semiconductor chip and a second gap filling layer surrounding an outer side surface of the second semiconductor chip. The first semiconductor chip includes a first backside insulating layer with second bonding pads. The second semiconductor chip includes a second front insulating layer with third bonding pads. The second bonding pads and the third bonding pads are directly bonded to each other.

公开(公告)号：US20250149458A1

公开(公告)日：2025-05-08

申请号：US18738439

申请日：2024-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyeong Park ,  SANG SUB SONG ,  SEOKBEOM YONG

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/16 ,  H10B80/00

Abstract: A semiconductor package comprises an interconnection structure including a plurality of signal wires and a plurality of ground wires, wherein the plurality of signal wires and the plurality of ground wires are alternately arranged in the first horizontal direction and extend in the second horizontal direction intersecting with the first horizontal direction; and a first semiconductor chip and a second semiconductor chip on the interconnection structure, wherein the interconnection structure includes first regions under the first semiconductor chip and under the second semiconductor chip and a second region between the first regions, and the plurality of signal wires connect the first semiconductor chip and the second semiconductor chip; wherein each of the plurality of signal wires has a first width in the first horizontal direction in the first region and a second width in the first horizontal direction in the second region, and the second width is greater than the first width.

公开(公告)号：US20250149430A1

公开(公告)日：2025-05-08

申请号：US18672870

申请日：2024-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungduk BAEK

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H01L25/18

Abstract: Provided is a semiconductor package including a first semiconductor chip including a substrate, interconnects, an insulating layer on the interconnects, first lower pads on the interconnects, and a first passivation layer on the first lower pads, and a second semiconductor chip including second upper pads contacting the first lower pads, a second passivation layer on the second upper pads and contacting the first passivation layer, second lower pads opposite to the second upper pads, and through-electrodes, wherein the first semiconductor chip has a first longer side extending in a first direction and a first shorter side extending in a second direction, the interconnects include intermediate conductors and connection conductors between the intermediate conductors and the first lower pads, a thickness of the connection conductors is greater than that of the intermediate conductors, and a number of the connection conductors is greater than that of the connection conductors.

公开(公告)号：US20250149422A1

公开(公告)日：2025-05-08

申请号：US19013464

申请日：2025-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a base substrate having a plurality of upper pads and a plurality of first and second lower pads, a semiconductor chip disposed on the base substrate and electrically connected to the plurality of upper pads, a solder resist layer having a plurality of openings exposing a region of each of the plurality of first and second lower pads, the exposed regions of the plurality of first and second lower pads having the same size, a plurality of first external connection conductors respectively disposed on the exposed regions of the plurality of first lower pads and having a first height and a first volume, and a plurality of second external connection conductors respectively disposed on the exposed regions of the plurality of second lower pads and having a second height, greater than the first height, and a second volume, greater than the first volume.

公开(公告)号：US20250149357A1

公开(公告)日：2025-05-08

申请号：US18640980

申请日：2024-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuntae Kim ,  Kyungyeol Kim ,  Jwahyeon Kim ,  Taesung Kim ,  Byunghyuck Ahn

IPC: H01L21/67 ,  B24B41/00 ,  H01L21/677 ,  H01L21/687

Abstract: An example apparatus for processing a wafer includes a grinder, a mounter, and a dock. The grinder is configured to grind a backside of the wafer. The mounter is configured to attach a ring to the wafer. The mounter is configured to remove a protection film from the wafer. The dock configured to dock the mounter with the grinder.

公开(公告)号：US20250149293A1

公开(公告)日：2025-05-08

申请号：US18747933

申请日：2024-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewon Jeong ,  Dongchan Jeon ,  Kyungsun Kim ,  Sungyeol Kim ,  Yongwon Cho

IPC: H01J37/32

Abstract: A plasma generation circuit includes a high frequency power source configured to generate a first high frequency current; a current divider comprising a first capacitor and a variable capacitor and configured to divide the first high frequency current into a second high frequency current and a third high frequency current; an antenna assembly comprising a center antenna connected to the current divider and through which the second high frequency current is configured to flow, and an edge antenna connected in to the current divider and through which the third high frequency current is configured to flow, the antenna assembly being configured to induce generation of an inductively coupled plasma; a first coil coupled inductor configured to allow the second high frequency current to flow therethrough; and a second coil coupled inductor configured to allow the third high frequency current to flow therethrough and adjacent to the first coil coupled inductor.