公开(公告)号：US10210776B2

公开(公告)日：2019-02-19

申请号：US15046069

申请日：2016-02-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Bruneau

IPC: H04L9/00 ,  H04L9/06 ,  G09C1/00

Abstract: A method of protecting a Rijndael-type algorithm executed by an electronic circuit against side channel attacks, wherein: each block of data to be encrypted or to be decrypted is masked with a first mask before a non-linear block substitution operation is applied based on a substitution box, and is then unmasked with a second mask after the substitution; and the substitution box is recalculated, block by block, before the non-linear operation is applied, the processing order of the blocks of the substitution box being submitted to a random permutation, commutative with the non-linear substitution operation.

公开(公告)号：US10199368B2

公开(公告)日：2019-02-05

申请号：US15436819

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/866 ,  H02H9/04

Abstract: An integrated circuit includes at least one input-output pad and a terminal intended to be connected to a source of a reference potential and further including a protection structure including a thyristor forward-connected between the pad and the terminal. The thyristor includes a first resistor between its cathode gate and the terminal. At least one Zener diode is disposed between the thyristor and the pad. The anode of the Zener diode is connected to the cathode gate of the thyristor and the cathode of the Zener diode is connected to the pad via at least one second resistor. The junction of the Zener diode is different from the junctions of the PNPN structure of the thyristor.

公开(公告)号：US20190027566A1

公开(公告)日：2019-01-24

申请号：US16036240

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L29/42324 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/7881

Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.

公开(公告)号：US20190027439A1

公开(公告)日：2019-01-24

申请号：US16037595

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L23/535 ,  H01L29/78 ,  H01L23/528 ,  H01L29/66 ,  H01L21/28 ,  H01L21/768

Abstract: An integrated circuit includes a substrate and an interconnect. A substrate zone is delineated by an insulating zone. A polysilicon region extends on the insulating zone and includes a strip part. An isolating region is situated between the substrate and the interconnect and covers the substrate zone and the polysilicon region. A first electrically conductive pad passes through the isolating region and has a first end in electrical contact with both the strip part and the substrate zone. A second end of the electrically conductive pad is in electrical contact with the interconnect. A second electrically conductive pad also passes through the isolating region to make electrical contact with another region. The first and second electrically conductive pads have equal or substantially equal cross sectional sizes, within a tolerance.

公开(公告)号：US10162728B2

公开(公告)日：2018-12-25

申请号：US15222368

申请日：2016-07-28

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Albert Martinez

IPC: G06F11/00 ,  G06F11/36 ,  G06F9/30

Abstract: A method for monitoring the execution of a program code by a monitoring program code may include storing instructions of the program code and instructions for monitoring the program code in the same program memory. Each instruction to be monitored and the associated monitoring instructions may be simultaneously extracted from the program memory, and the instruction to be monitored and the monitoring instructions may be executed.

公开(公告)号：US10157720B2

公开(公告)日：2018-12-18

申请号：US14517369

申请日：2014-10-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio di-Giacomo ,  Brice Arrazat

IPC: H01H61/02 ,  H01H1/58 ,  H01H9/02 ,  B81B3/00

Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.

公开(公告)号：US20180329721A1

公开(公告)日：2018-11-15

申请号：US16026233

申请日：2018-07-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Froidevaux ,  Jean-Michel Gril-Maffre ,  Jean-Pierre Leca

IPC: G06F9/4401 ,  H03K19/00 ,  G06F1/24 ,  G06F1/32 ,  G06F1/28

Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.

公开(公告)号：US20180321727A1

公开(公告)日：2018-11-08

申请号：US15883216

申请日：2018-01-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno Gailhard

IPC: G06F1/28 ,  H02H3/24 ,  G01R19/165 ,  H03K5/08

CPC classification number: G06F1/28 ,  G01R19/16552 ,  H02H1/06 ,  H02H3/05 ,  H02H3/24 ,  H02H3/247 ,  H02M2001/0006 ,  H03K5/082

Abstract: An integrated processing unit is supplied by a power supply voltage present at the terminals of a capacitor configured to supply a maximum permissible voltage drop. A periodic pulse signal is generated having a period that is less than or equal to a current period determined from the maximum permissible voltage drop and a current consumption of the processing unit. The power supply voltage is compared with a threshold voltage at the pulse rate of the periodic pulse signal. A control signal generated from that comparison is delivered to the processing unit and has a first value when the power supply voltage is greater than or equal to the threshold voltage and a second value when the power supply voltage is less than the threshold voltage.

公开(公告)号：US10049991B2

公开(公告)日：2018-08-14

申请号：US15596772

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/522 ,  H01L21/70 ,  H01L21/768 ,  H01L23/52 ,  H01L23/00 ,  H01L23/28 ,  H01L23/528 ,  H01L21/56

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.

公开(公告)号：US10049982B2

公开(公告)日：2018-08-14

申请号：US15596877

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.