Processor Operand Management Using Fusion Buffer

    公开(公告)号:US20250103338A1

    公开(公告)日:2025-03-27

    申请号:US18628403

    申请日:2024-04-05

    Applicant: Apple Inc.

    Abstract: Techniques are disclosed involving operand management using a fusion buffer. A processor includes operand management circuitry, where the operand management circuitry includes a fusion buffer, and execution circuitry. In one embodiment, the operand management circuitry is configured to detect a first storage instruction operation that is executable to store operand values usable by one or more consumer instruction operations and store the first storage instruction operation in the fusion buffer. In response to detecting a drop condition associated with the first storage instruction operation, the operand management circuitry is configured to remove the first storage instruction operation from the fusion buffer without forwarding the first storage instruction operation for execution. In response to detecting a buffer vacate condition and not detecting the drop condition the operand management circuitry is configured to forward the first storage instruction operation for execution by the execution circuitry.

    Matrix Multiplier Caching
    163.
    发明申请

    公开(公告)号:US20250103292A1

    公开(公告)日:2025-03-27

    申请号:US18426020

    申请日:2024-01-29

    Applicant: Apple Inc.

    Abstract: Techniques are disclosed relating to integrated circuits that support matrix operations. In various embodiments, an integrated circuit comprises a dot product accumulate circuit that includes a dot product circuit configured to determine a dot product of a first vector and a second vector, and an adder circuit coupled to an output of the dot product circuit and configured to add a result of the dot product and an accumulation value. The integrated circuit further includes an accumulator cache coupled to an input of the adder circuit and an output of the adder circuit. The accumulator cache is configured to provide the accumulation value to the adder circuit and store a result of the add as a subsequent accumulation value for a subsequent dot product accumulate operation.

    Power Management With Multiple Power Sources

    公开(公告)号:US20250103117A1

    公开(公告)日:2025-03-27

    申请号:US18392736

    申请日:2023-12-21

    Applicant: Apple Inc.

    Abstract: Techniques are disclosed relating to managing power allocation for component circuits coupled to one or more power sources. A system can include a plurality of component circuits, a plurality of power sources, and a power splitter circuit. The power splitter circuit may access, from programmable registers, a mapping between ones of the plurality of component circuits and ones of the plurality of power sources. The power splitter circuit may then allocate power to a given one of the plurality of component circuits based on one or more power budgets of one or more power sources that are mapped to the given component circuit as indicated by the mapping. In various cases, the power splitter circuit may determine that multiple power sources supply power to a particular component circuit and allocate power to the particular component circuit based on respective power budgets of the multiple power sources.

    ELECTRONIC DEVICE WITH BUMPER
    167.
    发明申请

    公开(公告)号:US20250102817A1

    公开(公告)日:2025-03-27

    申请号:US18826352

    申请日:2024-09-06

    Applicant: Apple Inc.

    Abstract: A head-mountable device can include a display frame, an optical component disposed within the display frame, a facial interface, and a rigid bumper connected to the display frame. The rigid bumper can be positioned between the display frame and the facial interface and can further define a gap between the optical component and the facial interface. The facial interface can also include a cushion layer that can be rated for applied loads in a first force range. Furthermore, a stop can be connected to the head-mountable display, wherein the stop can be rated for applied loads within a second force range that is higher than the first force range. The facial interface can further include a front surface facing toward the head-mountable display and a rear surface that can contact a face. A set of structural posts can also be attached to the head-mountable display and positioned adjacent to a forehead region and a maxilla region of a face, wherein a portion of each structural post of the set of structural posts can be embedded in the facial interface.

    ELECTRONIC DEVICE
    168.
    发明申请

    公开(公告)号:US20250102816A1

    公开(公告)日:2025-03-27

    申请号:US18826170

    申请日:2024-09-05

    Applicant: Apple Inc.

    Abstract: A head-mountable device can include a display, an arm, a bi-stable hinge connecting the arm to the display, the bi-stable hinge and the arm including an open position, a folded position, and a splay position. A first electronic component can be positionally fixed between the display and the bi-stable hinge, a second electronic component can be positioned distal to the bi-stable hinge, and a cable can connect the first electronic component and the second electronic component, the cable being routed through the bi-stable hinge.

    Electronic Devices with Transmitter-Receiver Array

    公开(公告)号:US20250102631A1

    公开(公告)日:2025-03-27

    申请号:US18673072

    申请日:2024-05-23

    Applicant: Apple Inc.

    Abstract: Disclosed are electronic devices that include an array of light emitting diodes and photosensors formed in a single semiconductor chip. The light emitting diodes may be structured as vertical exterior cavity surface-emitting laser diodes (VECSELs). The photosensors may be formed as resonant cavity photosensors (RCPDs). The VECSELs and the RCPDs of the array may be formed in a common set of semiconductor layers of the single semiconductor chip and separated by isolation regions formed in the common set of semiconductor layers. Also disclosed are dual chip transmitter-receiver systems including a first semiconductor chip having an array of both VECSELs and RCPDs formed in common set of semiconductor layers, and a second semiconductor chip electrically connected to the first semiconductor chip and including control circuitry to enable laser emission from the VECSELs and light reception by the RCPDs.

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