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公开(公告)号：US12217353B2
公开(公告)日：2025-02-04
申请号：US18490548
申请日：2023-10-19
Applicant: Apple Inc.
Inventor： Christopher A. Burns
Abstract: Techniques are disclosed relating to intersection tests for ray tracing in graphics processors. In some embodiments, test circuitry is configured to perform an intersection test based on traversal of an acceleration data structure that includes hierarchically-arranged bounding volumes for a graphics scene, where the test operates on: reduced-precision representations of rays that are quantized versions of initial representations of the rays and reduced-representatives of primitives that are quantized versions of initial representations of the primitives. The test may generate a first result for a first ray and a first primitive that indicates that a line coincident with the first ray definitively intersects the first primitive. The graphics processor may record an intersection for the first ray with the first primitive, based on the first result, without performing an intersection test for the first ray using the initial representation of the first ray and the first primitive.
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公开(公告)号：US12217350B2
公开(公告)日：2025-02-04
申请号：US17817742
申请日：2022-08-05
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , Christopher A. Burns , Justin A. Hensley , Luca Iuliano , Jonathan M. Redshaw
IPC: G06T15/06 , G06F9/38 , G06F9/48 , G06F9/50 , G06F16/22 , G06F30/31 , G06T1/20 , G06T1/60 , G06T15/00 , G06T17/00 , G06Q10/101 , G06Q50/04 , G06T17/10 , G16H40/67
Abstract: Disclosed techniques relate to acceleration data structure for ray intersection testing. In some embodiments, storage circuitry stores node data for a spatially organized acceleration data structure, including to store the following node information for a given node: origin coordinates for the node and, for a given child node of multiple child nodes, child information that includes: quantized bounding region information for a bounding region corresponding to the child node, where the quantized bounding region information encodes bounding region coordinates as offsets relative to the origin coordinates. Traversal circuitry may traverse multiple nodes of the data structure and determine whether a ray intersects a bounding region indicated by given a node of the data structure based on the node information. Disclosed techniques may provide substantial improvements to performance, data size, and power consumption.
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公开(公告)号：US20230325196A1
公开(公告)日：2023-10-12
申请号：US18299452
申请日：2023-04-12
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Liang-Kai Wang , Robert D. Kenney , Terence M. Potter
CPC classification number: G06F9/3887 , G06T1/60 , G06T1/20 , G06F9/30098
Abstract: Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline. In some embodiments, the routing circuitry may support a shift and fill instruction that facilitates storage of an arbitrary portion of a graphics frame in one or more registers.
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公开(公告)号：US20220036639A1
公开(公告)日：2022-02-03
申请号：US17103433
申请日：2020-11-24
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , Christopher A. Burns , Justin A. Hensley , Luca Iuliano , Jonathan M. Redshaw
Abstract: Disclosed techniques relate to ray intersection processing for ray tracing. In some embodiments, ray intersection circuitry traverses a spatially organized acceleration data structure and includes bounding region circuitry configured to test, in parallel, whether a ray intersects multiple different bounding regions indicated by a node of the data structure. Shader circuitry may execute a ray intersect instruction to invoke traversal by the ray intersect circuitry and the traversal may generate intersection results. The shader circuitry may shade intersected primitives based on the intersection results. Disclosed techniques that share processing between intersection circuitry and shader processors may improve performance, reduce power consumption, or both, relative to traditional techniques.
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公开(公告)号：US20210406031A1
公开(公告)日：2021-12-30
申请号：US17470682
申请日：2021-09-09
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Liang-Kai Wang , Robert D. Kenney , Terence M. Potter
Abstract: Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline. In some embodiments, the routing circuitry may support a shift and fill instruction that facilitates storage of an arbitrary portion of a graphics frame in one or more registers.
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Patent Agency Ranking
公开(公告)号：US20250103292A1
公开(公告)日：2025-03-27
申请号：US18426020
申请日：2024-01-29
Applicant: Apple Inc.
Inventor： David K. Li , Christopher A. Burns , Daniel E. Barnard , Evan R. Lissoos
Abstract: Techniques are disclosed relating to integrated circuits that support matrix operations. In various embodiments, an integrated circuit comprises a dot product accumulate circuit that includes a dot product circuit configured to determine a dot product of a first vector and a second vector, and an adder circuit coupled to an output of the dot product circuit and configured to add a result of the dot product and an accumulation value. The integrated circuit further includes an accumulator cache coupled to an input of the adder circuit and an output of the adder circuit. The accumulator cache is configured to provide the accumulation value to the adder circuit and store a result of the add as a subsequent accumulation value for a subsequent dot product accumulate operation.
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公开(公告)号：US20240281951A1
公开(公告)日：2024-08-22
申请号：US18651195
申请日：2024-04-30
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Casper R. W. van Benthem
CPC classification number: G06T7/0002 , G06T1/20 , G06T15/005 , G06T15/06 , G06T17/10 , G06T2207/20224
Abstract: Techniques are disclosed relating to testing whether a ray intersects a graphics primitive, e.g., for ray tracing. In some embodiments, intersection circuitry performs a reduced-precision conservative intersection test and shader circuitry performs an original-precision intersection test if the intersection circuitry indicates a hit. The intersection circuitry may quantize the ray (and may quantize the primitive or may receive a quantized representation of the primitive). The intersection circuitry then determines an intersection result for the reduced-precision test based on the quantized primitive data and quantized ray data. In various embodiments, disclosed techniques may improve performance or reduce power consumption by reducing the number of original-precision intersection tests that do not result in hits.
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公开(公告)号：US20230099114A1
公开(公告)日：2023-03-30
申请号：US17456503
申请日：2021-11-24
Applicant: Apple Inc.
Inventor： Christopher A. Burns
Abstract: Techniques are disclosed relating to intersection tests for ray tracing in graphics processors. In some embodiments, test circuitry is configured to perform intersection tests that operate on reduced-precision representations of rays that were generated by quantizing initial representations of the rays and reduced-precision representations of primitives that were generated by quantizing initial representations of the primitives. Some reduced-precision tests (e.g., for any-hit rays) may generate a definitive hit according to the initial representations. In this situation, graphics processing circuitry may record an intersection with the reduced-precision representation of the primitive for the ray based on the first result, without performing an intersection test for the first ray using the initial representation of the ray and the primitive. Disclosed techniques may advantageously reduce power consumption, improve performance, or both.
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公开(公告)号：US20220375155A1
公开(公告)日：2022-11-24
申请号：US17817742
申请日：2022-08-05
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , Christopher A. Burns , Justin A. Hensley , Luca Iuliano , Jonathan M. Redshaw
Abstract: Disclosed techniques relate to acceleration data structure for ray intersection testing. In some embodiments, storage circuitry stores node data for a spatially organized acceleration data structure, including to store the following node information for a given node: origin coordinates for the node and, for a given child node of multiple child nodes, child information that includes: quantized bounding region information for a bounding region corresponding to the child node, where the quantized bounding region information encodes bounding region coordinates as offsets relative to the origin coordinates. Traversal circuitry may traverse multiple nodes of the data structure and determine whether a ray intersects a bounding region indicated by given a node of the data structure based on the node information. Disclosed techniques may provide substantial improvements to performance, data size, and power consumption.
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10.发明授权公开(公告)号：US11335061B2
公开(公告)日：2022-05-17
申请号：US17103352
申请日：2020-11-24
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , Christopher A. Burns , Justin A. Hensley
Abstract: Disclosed techniques relate to an acceleration data structure for ray intersection with a many-to-many mapping between bounding regions and primitives. In some embodiments, one or more graphics processors access data for multiple graphics primitives in a graphics scene and generate a spatially organized data structure. Some nodes of the data structure indicate graphics primitives and some nodes indicate coordinates of bounding regions in the graphics scene. In some embodiments, the spatially organized data structure includes a node with a bounding region for which multiple primitives are indicated as children and also includes a primitive for which multiple bounding regions are indicated as parents. Disclosed techniques may generate bounding regions that closely fit primitives, which may reduce primitive testing for ray tracing. This in turn may increase performance or reduce power consumption relative to traditional techniques.
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