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    Method for managing a phase-locked loop and related circuit
    142.
    发明授权
    Method for managing a phase-locked loop and related circuit 有权

    公开(公告)号：US10530374B2

    公开(公告)日：2020-01-07

    申请号：US16289225

    申请日：2019-02-28

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Bruno Gailhard

    IPC: H03L7/10 ,  H03L7/14 ,  H03L7/089 ,  H03L7/099

    Abstract: A method can be used for managing the operation of a phase-locked loop. The loop includes an oscillator voltage controlled by a control signal and a phase comparator receiving a reference signal and a feedback signal which arises from the output signal of the oscillator. The method includes a detection of a possible absence of transitions on the feedback signal for a first duration and, in response to such an absence, a forcing of the lowering of the voltage of the control signal at least until a reappearance of transitions on the feedback signal.

    Electrically controllable integrated switch
    143.
    发明授权
    Electrically controllable integrated switch 有权

    公开(公告)号：US10510503B2

    公开(公告)日：2019-12-17

    申请号：US14985083

    申请日：2015-12-30

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio di-Giacomo ,  Brice Arrazat

    IPC: H01H59/00 ,  H01L27/06 ,  H01L21/822 ,  H01H1/00 ,  B81C1/00 ,  H01H57/00 ,  H01L23/522

    Abstract: Methods of forming and operating a switching device are provided. The switching device is formed in an interconnect, the interconnect including a plurality of metallization levels, and has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.

    INTEGRATED CIRCUIT COMPRISING A CAPACITIVE ELEMENT, AND MANUFACTURING METHOD
    144.
    发明申请
    INTEGRATED CIRCUIT COMPRISING A CAPACITIVE ELEMENT, AND MANUFACTURING METHOD 审中-公开

    公开(公告)号：US20190341446A1

    公开(公告)日：2019-11-07

    申请号：US16400286

    申请日：2019-05-01

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Abderrezak MARZAKI

    IPC: H01L49/02 ,  H01L27/11517 ,  H01L29/06

    Abstract: A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.

    Method for writing in an EEPROM memory and corresponding device
    146.
    发明授权
    Method for writing in an EEPROM memory and corresponding device 有权

    公开(公告)号：US10446235B2

    公开(公告)日：2019-10-15

    申请号：US15984779

    申请日：2018-05-21

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： François Tailliet

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/788

    Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

    MOTOR CONTROL SYSTEM
    149.
    发明申请
    MOTOR CONTROL SYSTEM 审中-公开

    公开(公告)号：US20190267922A1

    公开(公告)日：2019-08-29

    申请号：US16281604

    申请日：2019-02-21

    Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

    Inventor： Gwenael MAILLET ,  Jean-Louis LABYRE ,  Gilles BAS

    IPC: H02P7/29 ,  G06K19/07 ,  G05B19/042

    Abstract: Control over the operation of an electrically-controlled motor is supported by an interface circuit between the electrically-controlled motor and a near-field radio frequency communication controller. The interface circuit includes a first circuit that receives at least one control set point through a near-field radio frequency communication issued by the near-field radio frequency communication controller. A second circuit of the interface generates one or more electric signals in pulse width modulation based on the control set point.

    STANDARD INTEGRATED CELL WITH CAPACITIVE DECOUPLING STRUCTURE
    150.
    发明申请
    STANDARD INTEGRATED CELL WITH CAPACITIVE DECOUPLING STRUCTURE 审中-公开

    公开(公告)号：US20190237589A1

    公开(公告)日：2019-08-01

    申请号：US16259424

    申请日：2019-01-28

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Abderrezak MARZAKI

    IPC: H01L29/94 ,  H01L29/66 ,  H01L27/06

    CPC classification number: H01L29/945 ,  H01L27/0629 ,  H01L27/0733 ,  H01L29/66181

    Abstract: A standard integrated cell includes a semiconductor region with a functional domain for logic circuits including a transistor and an adjacent continuity domain that extends out to an edge of the standard integrated cell. The edge is configured to be adjacent to another continuity domain of another standard integrated cell. The standard integrated cell further includes at capacitive element. This capacitive element may be housed in the continuity domain, for example at or near the edge. Alternatively, the capacitive element may be housed at a location which extends around a substrate region of the transistor.

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