公开(公告)号：US08217472B2

公开(公告)日：2012-07-10

申请号：US13178362

申请日：2011-07-07

Applicant: Richard J. Carter ,  George J. Kluth ,  Michael J. Hargrove

Inventor： Richard J. Carter ,  George J. Kluth ,  Michael J. Hargrove

IPC: H01L29/772

CPC classification number: H01L21/76232

Abstract: A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.

Abstract translation: 这里提供一种制造半导体器件的方法，其中所得半导体器件中的宽度效应降低。 该方法包括提供具有半导体材料的衬底，在半导体材料中形成隔离沟槽，并用衬垫材料衬里隔离沟槽，衬垫材料基本上抑制其上形成高k材料。 然后用绝缘材料填充衬里的沟槽。 此后，在绝缘材料的至少一部分上以及半导体材料的至少一部分上形成一层高k栅极材料。 衬垫材料分隔高k栅极材料层，其阻止氧在半导体材料的有源区上迁移。

公开(公告)号：US20120168881A1

公开(公告)日：2012-07-05

申请号：US13142591

申请日：2011-01-27

Applicant: Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Huicai Zhong ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

Abstract translation: 本发明提供一种半导体器件及其制造方法。 制造半导体器件的方法包括：提供其上形成有栅极叠层结构并具有{100}晶体指数的硅衬底; 形成层叠所述硅衬底的顶表面的层间电介质层; 在所述层间介质层和/或所述栅堆叠结构中形成第一沟槽，所述第一沟槽具有沿着晶体方向并且垂直于所述栅堆叠结构的延伸方向; 以及用第一介电层填充所述第一沟槽，其中所述第一介电层是拉伸应力介电层。 本发明通过使用简单的工艺在沟道区域的横向上引入拉伸应力，这提高了半导体器件的响应速度和性能。

公开(公告)号：US20120168865A1

公开(公告)日：2012-07-05

申请号：US13144903

申请日：2011-02-25

Applicant: Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

Inventor： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/78648 ,  H01L29/66545 ,  H01L29/66628

Abstract: The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved.

Abstract translation: 本发明涉及晶体管及其制造方法。 根据本发明的实施例的晶体管可以包括：至少包括晶体管的背栅极，绝缘层和顺序层叠的半导体层的衬底，其中晶体管的背栅极用于调节晶体管的阈值电压 晶体管; 形成在所述半导体层上的栅极堆叠，其中所述栅极堆叠包括形成在所述栅极电介质上的栅极电介质和栅电极; 形成在栅叠层的侧壁上的间隔物; 以及分别位于栅极堆叠的两侧的源极区域和漏极区域，其中栅极叠层的高度低于间隔物的高度。 该晶体管能够降低栅极叠层的高度，从而提高晶体管的性能。

公开(公告)号：US20120146112A1

公开(公告)日：2012-06-14

申请号：US13396291

申请日：2012-02-14

Applicant: Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  John Edward Sheets, II

Inventor： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  John Edward Sheets, II

IPC: H01L29/772

CPC classification number: H01L29/785 ,  H01L29/045 ,  H01L29/66818

Abstract: Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.

Abstract translation: 本发明的实施例提供了Fin场效应晶体管（FinFET）中的相对均匀的宽度鳍片及其形成方法。 翅片结构可以形成为使翅片结构的侧壁部分的表面垂直于第一结晶方向。 翅片结构端部的锥形区域可以垂直于第二晶体方向。 可以对翅片结构进行晶体依赖蚀刻。 晶体依赖蚀刻可以相对较快地从第二晶体方向垂直于翅片的部分去除材料，从而形成相对均匀的宽度鳍片结构。

公开(公告)号：US20120146107A1

公开(公告)日：2012-06-14

申请号：US13274367

申请日：2011-10-17

Applicant: Jong-Won LIM ,  Hokyun Ahn ,  Dong Min Kang ,  Woojin Chang ,  Hae Cheon Kim ,  Eun Soo Nam

Inventor： Jong-Won LIM ,  Hokyun Ahn ,  Dong Min Kang ,  Woojin Chang ,  Hae Cheon Kim ,  Eun Soo Nam

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L29/2003 ,  H01L29/40 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device according to an exemplary embodiment of the present disclosure, at the time of forming a source electrode, a drain electrode, a field plate electrode, and a gate electrode on a substrate having a heterojunction structure such as AlGaN/GaN, the field plate electrode made of the same metal as the gate electrode is formed on the side surface of a second support part positioned below a head part of the gate electrode so as to prevent the gate electrode from collapsing and improve high-frequency and high-voltage characteristic of the semiconductor device.

Abstract translation: 公开了一种半导体器件及其制造方法。 在根据本公开的示例性实施例的半导体器件中，在具有诸如AlGaN / GaN的异质结结构的衬底上形成源电极，漏电极，场板电极和栅电极时， 由与栅电极相同的金属制成的场板电极形成在位于栅电极的头部下方的第二支撑部分的侧表面上，以防止栅电极塌陷并改善高频和高电压 半导体器件的特性。

公开(公告)号：US20120139061A1

公开(公告)日：2012-06-07

申请号：US12958607

申请日：2010-12-02

Applicant: Ravikumar Ramachandran ,  Ying Li ,  Richard S. Wise

Inventor： Ravikumar Ramachandran ,  Ying Li ,  Richard S. Wise

IPC: H01L29/772 ,  H01L21/283

CPC classification number: H01L29/78 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

Abstract: A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.

Abstract translation: 替代栅极堆叠的导电顶表面通过至少一个蚀刻相对于平坦化介电层的顶表面凹陷。 介电覆盖层沉积在平坦化电介质层和替代栅极堆叠的顶表面上，使得替代栅极堆叠上的介电顶盖层的一部分的顶表面相对于上述电介质层的另一部分垂直凹陷 平坦化介电层。 电介质覆盖层的垂直偏移可以与选择性通孔蚀刻工艺结合使用以形成自对准接触结构。

公开(公告)号：US20120139027A1

公开(公告)日：2012-06-07

申请号：US13238368

申请日：2011-09-21

Applicant: Byoung-keun Son ,  Chang-hyun Lee

Inventor： Byoung-keun Son ,  Chang-hyun Lee

IPC: H01L29/78 ,  H01L29/772

CPC classification number: H01L29/7926 ,  H01L21/2255

Abstract: A vertical structure non-volatile memory device includes a channel region that vertically extends on a substrate. A memory cell string vertically extends on the substrate along a first wall of the channel regions, and includes at least one selection transistor and at least one memory cell. An impurity providing layer is disposed on a second wall of the channel region and includes impurities.

Abstract translation: 垂直结构的非易失性存储器件包括在衬底上垂直延伸的沟道区域。 存储单元串沿着沟道区的第一壁在衬底上垂直延伸，并且包括至少一个选择晶体管和至少一个存储单元。 杂质提供层设置在沟道区的第二壁上并且包括杂质。

公开(公告)号：US20120126340A1

公开(公告)日：2012-05-24

申请号：US12949272

申请日：2010-11-18

Applicant: Donald R. DISNEY

Inventor： Donald R. DISNEY

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/2652 ,  H01L29/1083 ,  H01L29/6659

Abstract: An MOS transistor includes a doping profile that selectively increases the dopant concentration of the body region. The doping profile has a shallow portion that increases the dopant concentration of the body region just under the surface of the transistor under the gate, and a deep portion that increases the dopant concentration of the body region under the source and drain regions. The doping profile may be formed by implanting dopants through the gate, source region, and drain region. The dopants may be implanted in a high energy ion implant step through openings of a mask that is also used to perform another implant step. The dopants may also be implanted through openings of a dedicated mask.

Abstract translation: MOS晶体管包括选择性地增加身体区域的掺杂剂浓度的掺杂分布。 掺杂分布具有浅部分，其增加正好在栅极下的晶体管的表面下方的体区的掺杂剂浓度，以及增加源极和漏极区下的体区的掺杂剂浓度的深部。 可以通过在栅极，源极区和漏极区注入掺杂剂来形成掺杂分布。 掺杂剂可以通过掩模的开口在高能离子注入步骤中植入，掩模的开口也用于执行另一个注入步骤。 掺杂剂也可以通过专用掩模的开口植入。

公开(公告)号：US20120119273A1

公开(公告)日：2012-05-17

申请号：US12946915

申请日：2010-11-16

Applicant: Brian M. Czabaj ,  James V. Hart, III ,  William J. Murphy ,  James S. Nakos

Inventor： Brian M. Czabaj ,  James V. Hart, III ,  William J. Murphy ,  James S. Nakos

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/66477 ,  H01L29/6684 ,  H01L29/78391

Abstract: A ferro-electric random access memory (FRAM) chip, including a substrate; a first dielectric layer over the substrate; a gate over the first dielectric layer; a first aluminum oxide layer over the first dielectric layer and the gate; a second dielectric layer over the first aluminum oxide layer; a trench through the second dielectric layer and the first aluminum oxide layer to the gate; a hydrogen barrier liner over the second dielectric layer and lining the trench, and contacting the gate; and a silicon dioxide plug over the hydrogen barrier liner substantially filling the trench.

Abstract translation: 铁电随机存取存储器（FRAM）芯片，包括衬底; 衬底上的第一电介质层; 第一介电层上的栅极; 在第一介电层和栅极上的第一氧化铝层; 在第一氧化铝层上的第二介电层; 通过第二介电层和第一氧化铝层到沟槽的沟槽; 在所述第二电介质层上方的氢阻挡衬垫，并且衬套所述沟槽，并且与所述栅极接触; 以及基本上填充所述沟槽的氢阻挡衬里上的二氧化硅塞。

公开(公告)号：US20120112252A1

公开(公告)日：2012-05-10

申请号：US13380380

申请日：2011-02-27

Applicant: Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

Inventor： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L23/485 ,  H01L21/76804 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which lies in covering a first dielectric layer with a second dielectric layer, forming a first contact hole with a small inner diameter within the second dielectric layer first, then etching the first dielectric layer to form a second contact hole with a much great inner diameter, and finally filling a conductive material into the first contact hole and the second contact hole to form contact plugs. Accordingly, the present invention further provides a semiconductor structure favorable for reducing contact resistance.

Abstract translation: 本发明提供了一种制造半导体结构的方法，该半导体结构覆盖第一介电层与第二介电层，首先在第二电介质层内形成具有小内径的第一接触孔，然后蚀刻第一介电层至 形成具有非常大的内径的第二接触孔，最后将导电材料填充到第一接触孔和第二接触孔中以形成接触塞。 因此，本发明还提供有利于降低接触电阻的半导体结构。