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公开(公告)号：US11444432B2
公开(公告)日：2022-09-13
申请号：US16780761
申请日：2020-02-03
Inventor： Jonathan Ephraim David Hurwitz , Davide Portaluppi
IPC: H01S5/042 , H01S5/183 , H01S5/00 , G01S7/484 , G01S7/4865 , G01S17/894
Abstract: Time-of-flight (ToF) systems which use pulsed laser diodes, are required to measure distances with high level of precision and control. The present disclosure provides a method and a corresponding system for controlling a temporal response of a laser diode, in particular pulsed laser diodes. In particular, the present disclosure provides a method and a related system for driving a laser diode so as to obtain predominantly a peak pulse response while minimising or completely avoiding the post-peak response in a temporal response of the laser diode.
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公开(公告)号：US11437963B2
公开(公告)日：2022-09-06
申请号：US17031426
申请日：2020-09-24
Inventor： Gabriele Manganaro , Athanasios Ramkaj , Filip Tavernier
Abstract: High-performance radio frequency analog-to-digital converters (RF ADCs) demand high bandwidth, high linearity, and low noise input amplifiers. A Class-AB amplifier, including common-gate transistor devices and common-source transistor devices operating in parallel, offers high bandwidth and high linearity, while offering lower power operation when compared to Class-A amplifiers. The Class-AB amplifier can be followed by a Class-AB unity gain buffer comprising common-source transistor devices to provide additional isolation for the RF ADC from the circuitry preceding the Class-AB amplifier.
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公开(公告)号：US11418369B2
公开(公告)日：2022-08-16
申请号：US16940937
申请日：2020-07-28
Inventor： Andrew J. Gardner
Abstract: A PoDL system that uses a center-tapped transformer, for galvanic isolation of the PHY, has AC-coupling capacitors in series between the transmission wires and the transformer's secondary windings for blocking DC voltages generated by a PSE power supply. The center tap is conventionally connected to ground. As a result, one capacitor sees the full VPSE voltage across it, and the other capacitor sees approximately 0 V across it. Since the effective value of a ceramic capacitor significantly reduces with increasing DC bias voltages across it, the effective values of the capacitors will be very different, resulting in unbalanced data paths. This can lead to conversion of common mode noise and corrupt the data. To avoid this, a resistor divider is used to generate VPSE/2, and this voltage is applied to the center tap of the transformer. Therefore, the DC voltage across each capacitor is approximately VPSE/2, so their values remain equal.
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公开(公告)号：US11415678B2
公开(公告)日：2022-08-16
申请号：US15870340
申请日：2018-01-12
Inventor： Savas Tokmak , Sinan Alemdar
IPC: G01S7/486 , G01S7/4861 , G01S17/931 , G01S17/10
Abstract: A receiver for a light detection and range finding system is disclosed. The receiver can include an optoelectrical device to receive a pulse of light reflected from a target and to convert the pulse of light to a current pulse. The receiver can also include a transimpedance amplifier (TIA) to convert the current pulse to a voltage pulse. The receiver can also include a tunable filter that has an input coupled to an output of the TIA. The tunable filter can have a frequency response that is adjustable. The TIA and the tunable filter can be disposed on a single integrated circuit (IC) die.
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公开(公告)号：US20220255551A1
公开(公告)日：2022-08-11
申请号：US17734346
申请日：2022-05-02
Inventor： Alexander LEONARD , Lu WU , Christopher MAYER , Gord ALLAN
Abstract: Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.
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Patent Agency Ranking
公开(公告)号：US11411490B2
公开(公告)日：2022-08-09
申请号：US16577146
申请日：2019-09-20
Inventor： William L. Walter
IPC: H02M3/07
Abstract: Charge pumps with accurate output current limiting are provided herein. In certain embodiments, a charge pump includes an output terminal for providing a regulated output voltage, a switched capacitor, and switches that control connectivity of the switched capacitor to selectively charge or discharge the switched capacitor. The switches are operable in two or more phases including a charging phase in which the switched capacitor is charged with a charging current and a discharging phase in which the switched capacitor is coupled to the output terminal. The charge pump further includes an output current limiting circuit that controls the charging current to limit an amount of output current delivered by the charge pump to the output terminal. The output current limiting circuit limits the output current based on comparing a reference signal to an integral of an observation current that changes in relation to the charging current.
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公开(公告)号：US20220247396A1
公开(公告)日：2022-08-04
申请号：US17443233
申请日：2021-07-22
Inventor： Mohamed A. Shehata , James Breslin , Michael F. Keaveney , Hyman Shanan
Abstract: Rotary traveling wave oscillator-based (RTWO-based) frequency multipliers are provided herein. In certain embodiments, an RTWO-based frequency multiplier includes an RTWO that generates a plurality of clock signal phases of a first frequency, and an edge combiner that processes the clock signal phases to generate an output clock signal having a second frequency that is a multiple of the first frequency. The edge combiner can be implemented as a logic-based combining circuit that combines the clock signal phases from the RTWO. For example, the edge combiner can include parallel stacks of transistors operating on different clock signal phases, with the stacks selectively activating based on timing of the clock signal phases to generate the output clock signal of multiplied frequency.
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公开(公告)号：US20220239262A1
公开(公告)日：2022-07-28
申请号：US17659059
申请日：2022-04-13
Inventor： Ahmed I. Khalil , Patrick Pratt
Abstract: Apparatus and methods provide predistortion for a phased array. Radio frequency (RF) sample signals from phased array elements are provided along return paths and are combined by a hardware RF combiner. Phase shifters are adjusted such that the RF sample signals are phase-aligned when combined. Adaptive adjustment of predistortion for the amplifiers of the phased array can be based on a signal derived from the combined RF sample signals.
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公开(公告)号：US20220231707A1
公开(公告)日：2022-07-21
申请号：US17715761
申请日：2022-04-07
Inventor： Alexander LEONARD , Satishchandra G. RAO , Christopher MAYER , Brian Kenneth NEELY
Abstract: A radio timing controller equipped with one or more sequence controllers is disclosed. Sequence controllers enable high degree of programmability of the radio timing controller, e.g., in terms of the number of general purpose input/outputs (GPIOs), mapping of GPIOs to specific radio controls, setting of the radio control output states, timing to sequence events at radio symbol boundaries, etc.
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公开(公告)号：US20220221420A1
公开(公告)日：2022-07-14
申请号：US17712644
申请日：2022-04-04
Inventor： Michael COLN , Mark Daniel de Leon ALEA
IPC: G01N27/327 , G01N33/487 , G01N27/00 , H03K3/03 , G01N27/414 , G01N33/497
Abstract: Embodiments of the present disclosure relate to various methods and example systems for carrying out analog-to-digital conversion of data acquired by arrays of nanogap sensors. The nanogap sensors described herein may operate as molecular sensors to help identify chemical species through electrical measurements using at least a pair of electrodes separated by a nanogap. In general, the methods and systems proposed herein rely on digitizing the signal as the signal is being integrated, and then integrating the digitized results. With such methods, the higher sample rate used in the digitizer reduces the charge per quantization and, therefore, the size of sampling capacitors used. Consequently, sampling capacitors may be made factors of magnitude smaller, requiring less valuable space on a chip compared to sampling capacitors used in conventional nanogap sensor arrays.
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