公开(公告)号：US20120273902A1

公开(公告)日：2012-11-01

申请号：US13094953

申请日：2011-04-27

Applicant: Kun-Hsien LIN ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

Inventor： Kun-Hsien LIN ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L21/31144 ,  H01L21/28008 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: A gate stack structure with an etch stop layer is provided. The gate stack structure is formed over a substrate. A spacer is formed on a sidewall of the gate stack structure. The gate stack structure includes a gate dielectric layer, a barrier layer, a repair layer and the etch stop layer. The gate dielectric layer is formed on the substrate. The barrier layer is formed on the gate dielectric layer. The barrier layer and an inner sidewall of the spacer collectively define a trench. The repair layer is formed on the barrier layer and an inner wall of the trench. The etch stop layer is formed on the repair layer.

Abstract translation: 提供具有蚀刻停止层的栅极堆叠结构。 栅极堆叠结构形成在衬底上。 在栅堆叠结构的侧壁上形成间隔物。 栅极堆叠结构包括栅极介电层，阻挡层，修复层和蚀刻停止层。 栅极电介质层形成在基板上。 阻挡层形成在栅介质层上。 隔离层和间隔物的内侧壁共同限定沟槽。 修复层形成在阻挡层和沟槽的内壁上。 蚀刻停止层形成在修复层上。

公开(公告)号：US20120273850A1

公开(公告)日：2012-11-01

申请号：US13346947

申请日：2012-01-10

Applicant: Sung Kil CHUN

Inventor： Sung Kil CHUN

IPC: H01L29/772 ,  H01L21/302 ,  H01L21/336

CPC classification number: H01L29/7853 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/772

Abstract: A semiconductor device and a method for fabricating the same are disclosed. A fin of the semiconductor device including a fin-shaped channel region is configured in the form of a non-uniform structure, and a leakage current caused by the electric field effect generated in the semiconductor device is prevented from being generated, resulting in an increased operation stability of the semiconductor device.

Abstract translation: 公开了一种半导体器件及其制造方法。 包括鳍状沟道区域的半导体器件的鳍被配置为不均匀结构的形式，并且防止由在半导体器件中产生的电场效应引起的漏电流被产生，导致增加 半导体器件的操作稳定性。

公开(公告)号：US20120267716A1

公开(公告)日：2012-10-25

申请号：US13090338

申请日：2011-04-20

Applicant: Ching-Hung KAO ,  Sheng-Hsiong Yang

Inventor： Ching-Hung KAO ,  Sheng-Hsiong Yang

IPC: H01L29/772 ,  H01L29/06

CPC classification number: H01L29/66689 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7816

Abstract: A high voltage metal oxide semiconductor device with low on-state resistance is provided. A multi-segment isolation structure is arranged under a gate structure and beside a drift region for blocking the current from directly entering the drift region. Due to the multi-segment isolation structure, the path length from the body region to the drift region is increased. Consequently, as the breakdown voltage applied to the gate structure is increased, the on-state resistance is reduced.

Abstract translation: 提供具有低导通电阻的高电压金属氧化物半导体器件。 多段隔离结构被布置在栅极结构之下并且在漂移区旁边，用于阻止电流直接进入漂移区。 由于多段隔离结构，从身体区域到漂移区域的路径长度增加。 因此，随着施加到栅极结构的击穿电压增加，导通电阻降低。

公开(公告)号：US20120261727A1

公开(公告)日：2012-10-18

申请号：US13380061

申请日：2011-02-27

Applicant: Huicai Zhong ,  Qingqing Liang

Inventor： Huicai Zhong ,  Qingqing Liang

IPC: H01L29/772 ,  H01L21/768

CPC classification number: H01L29/78 ,  H01L21/76895 ,  H01L21/76897

Abstract: A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth.

Abstract translation: 提供半导体器件和用于制造半导体器件的局部互连结构的方法。 该方法包括在半导体衬底上的栅极的两侧上的侧壁间隔件和外侧壁间隔件之间形成可移除的牺牲侧壁间隔件，以及在侧壁间隔件和外侧壁之间的局部互连结构中的源极/漏极区域处形成接触通孔 在去除牺牲侧壁间隔物之后立即在栅极的同一侧上间隔开。 一旦源极/漏极通孔填充有导电材料以形成接触孔，接触孔的高度应与栅极的高度相同。 在本地互连结构中，建立后续的第一金属布线层和源极/漏极区域或较低电平的栅极区域之间的电连接的接触通孔应制成相同的深度。

公开(公告)号：US20120256262A1

公开(公告)日：2012-10-11

申请号：US13439356

申请日：2012-04-04

Applicant: Maud VINET ,  Laurent GRENOUILLET ,  Yannick LE TIEC ,  Nicolas POSSEME

Inventor： Maud VINET ,  Laurent GRENOUILLET ,  Yannick LE TIEC ,  Nicolas POSSEME

IPC: H01L29/772 ,  H01L21/768

CPC classification number: H01L29/78648 ,  H01L21/743 ,  H01L21/76283

Abstract: The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode.

Abstract translation: 场效应晶体管包括依次包括导电支撑衬底，电绝缘层和半导体材料层的衬底。 对置电极形成在支撑基板的面向半导体材料层的第一部分中。 绝缘图案围绕半导体材料层以描绘第一有源区域并且其部分地穿透到支撑层中以描绘第一部分。 导电接触通过绝缘图案从与对电极接触的第一侧表面穿过第二表面。 触点电连接到对电极。

公开(公告)号：US08283733B2

公开(公告)日：2012-10-09

申请号：US12940507

申请日：2010-11-05

Applicant: Zhong Dong ,  Ching-Hwa Chen

Inventor： Zhong Dong ,  Ching-Hwa Chen

IPC: H01L29/36 ,  H01L29/772

CPC classification number: H01L21/324 ,  H01L21/28167 ,  H01L21/28238 ,  H01L29/78

Abstract: Performance of field effect transistors and other channel dependent devices formed on a monocrystalline substrate is improved by carrying out a high temperature anneal in a nitrogen releasing atmosphere while the substrate is coated by a sacrificial oxide coating containing easily diffusible atoms that can form negatively charged ions and can diffuse deep into the substrate. In one embodiment, the easily diffusible atoms comprise at least 5% by atomic concentration of chlorine atoms in the sacrificial oxide coating and the nitrogen releasing atmosphere includes NO. The high temperature anneal is carried out for less than 10 hours at a temperature less than 1100° C.

Abstract translation: 通过在氮气释放气氛中进行高温退火，同时通过包含容易扩散的原子的牺牲氧化物涂层涂覆基底，从而改善在单晶衬底上形成的场效应晶体管和其它通道相关器件的性能，所述牺牲氧化物涂层可形成带负电荷的离子， 可以深层扩散到底物中。 在一个实施方案中，容易扩散的原子在牺牲氧化物涂层中包含至少5％的原子浓度的氯原子，并且氮气释放气氛包括NO。 高温退火在低于1100℃的温度下进行少于10小时。

公开(公告)号：US20120248414A1

公开(公告)日：2012-10-04

申请号：US13292285

申请日：2011-11-09

Applicant: Sun-kook Kim ,  Woong Choi ,  Yong-wan Jin

Inventor： Sun-kook Kim ,  Woong Choi ,  Yong-wan Jin

IPC: H01L29/772 ,  H01L21/336 ,  B82Y40/00 ,  B82Y99/00

CPC classification number: H01L29/1606 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/1054 ,  H01L29/66431 ,  H01L29/7782 ,  H01L29/7831 ,  Y10S977/734

Abstract: An example embodiment relates to a semiconductor device including a semiconductor element. The semiconductor element may include a plurality of unit layers spaced apart from each other in a vertical direction. Each unit layer may include a patterned graphene layer. The patterned graphene layer may be a layer patterned in a nanoscale. The patterned graphene layer may have a nanomesh or nanoribbon structure. The semiconductor device may be a transistor or a diode. An example embodiment relates to a method of making a semiconductor device including a semiconductor element.

Abstract translation: 示例性实施例涉及包括半导体元件的半导体器件。 半导体元件可以包括在垂直方向上彼此间隔开的多个单元层。 每个单位层可以包括图案化的石墨烯层。 图案化的石墨烯层可以是以纳米尺度图案化的层。 图案化石墨烯层可以具有纳米级或纳米级结构。 半导体器件可以是晶体管或二极管。 示例性实施例涉及制造包括半导体元件的半导体器件的方法。

公开(公告)号：US20120241863A1

公开(公告)日：2012-09-27

申请号：US13052338

申请日：2011-03-21

Applicant: Teng-Chun TSAI ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

Inventor： Teng-Chun TSAI ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7833

Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.

Abstract translation: 鳍状场效应晶体管结构包括衬底，鳍状沟道和高k金属栅极。 高k金属栅极形成在基板和鳍状通道上。 制造鳍式场效应晶体管结构的工艺包括以下步骤。 首先，在基板和散热片通道的表面上形成多晶硅伪栅极结构。 通过使用多晶硅伪栅极结构作为掩模，在鳍式沟道中形成源/漏区。 在去除多晶硅伪栅极结构之后，依次形成高k电介质层和金属栅极层。 然后，在具有金属栅极层的基板上进行平坦化处理，直到第一介电层露出为止，从而产生高k金属栅极。

公开(公告)号：US20120228676A1

公开(公告)日：2012-09-13

申请号：US13043323

申请日：2011-03-08

Applicant: Chung Foong Tan ,  Eng Huat Toh ,  Jae Gon Lee ,  Sanford Chu

Inventor： Chung Foong Tan ,  Eng Huat Toh ,  Jae Gon Lee ,  Sanford Chu

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7853 ,  H01L29/66795

Abstract: A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.

Abstract translation: FinFET（p沟道）器件形成为具有倾斜或成角度的侧壁（例如，金字塔形或梯形形状的横截面形状）的翅片结构。 当使用具有（100）表面取向的常规半导体衬底时，翅片结构以一种（凹槽蚀刻）形成，其导致具有（111）表面取向的倾斜或成角度的侧壁。 与具有垂直侧壁的常规翅片结构相比，该特性显着增加了空穴迁移率。

公开(公告)号：US20120228671A1

公开(公告)日：2012-09-13

申请号：US13263227

申请日：2011-08-25

Applicant: Jing Wang ,  Jun Xu ,  Lei Guo

Inventor： Jing Wang ,  Jun Xu ,  Lei Guo

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/78684 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/78603 ,  H01L29/78618

Abstract: A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a SiN stress cap layer covering the gate stack to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.

Abstract translation: 提供了一种应变绝缘体上的结构，包括：硅衬底，其中在硅衬底的表面上形成氧化物绝缘层; 形成在所述氧化物绝缘层上的Ge层，其中在所述Ge层和所述氧化物绝缘层之间形成第一钝化层; 形成在Ge层上的栅极叠层，形成在栅叠层下方的沟道区，以及形成在沟道区的侧面上的源极和漏极; 以及覆盖栅极堆叠以在沟道区域中产生应变的SiN应力覆盖层。 此外，还提供了用于形成应变的绝缘体上Ge的结构的方法。