公开(公告)号：US20120267716A1

公开(公告)日：2012-10-25

申请号：US13090338

申请日：2011-04-20

Applicant: Ching-Hung KAO ,  Sheng-Hsiong Yang

Inventor： Ching-Hung KAO ,  Sheng-Hsiong Yang

IPC: H01L29/772 ,  H01L29/06

CPC classification number: H01L29/66689 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7816

Abstract: A high voltage metal oxide semiconductor device with low on-state resistance is provided. A multi-segment isolation structure is arranged under a gate structure and beside a drift region for blocking the current from directly entering the drift region. Due to the multi-segment isolation structure, the path length from the body region to the drift region is increased. Consequently, as the breakdown voltage applied to the gate structure is increased, the on-state resistance is reduced.

Abstract translation: 提供具有低导通电阻的高电压金属氧化物半导体器件。 多段隔离结构被布置在栅极结构之下并且在漂移区旁边，用于阻止电流直接进入漂移区。 由于多段隔离结构，从身体区域到漂移区域的路径长度增加。 因此，随着施加到栅极结构的击穿电压增加，导通电阻降低。

公开(公告)号：US20130277728A1

公开(公告)日：2013-10-24

申请号：US13451625

申请日：2012-04-20

Applicant: Ching-Hung KAO

Inventor： Ching-Hung KAO

IPC: H01L29/788 ,  H01L21/28

CPC classification number: H01L27/11534 ,  H01L21/28273 ,  H01L21/823456 ,  H01L29/4983 ,  H01L29/78

Abstract: The present disclosure provides a fabricating method of a semiconductor chip which includes the following steps. First, a substrate is provided. The substrate defines a memory unit region and a peripheral logic region. Then, a first spacer is formed around a stack structure of the memory unit region. The first space includes a first silicon oxide layer and the first silicon oxide layer directly contacts with the stack structure. After that, a silicon nitride layer is formed on both the first spacer and the peripheral logic region. Finally, the additional silicon nitride layer on the first spacer is removed but portions of the additional silicon nitride layer around gate structures in the peripheral logic region are remained.

Abstract translation: 本公开提供了一种半导体芯片的制造方法，包括以下步骤。 首先，提供基板。 衬底限定存储器单元区域和外围逻辑区域。 然后，围绕存储单元区域的堆叠结构形成第一间隔物。 第一空间包括第一氧化硅层，并且第一氧化硅层与堆叠结构直接接触。 之后，在第一间隔物和周边逻辑区域上形成氮化硅层。 最后，去除第一间隔物上的另外的氮化硅层，但是留下外围逻辑区域中的栅极结构周围的附加氮化硅层的部分。

公开(公告)号：US20130069190A1

公开(公告)日：2013-03-21

申请号：US13238076

申请日：2011-09-21

Applicant: Ching-Hung KAO ,  Hsin-Ping Wu

Inventor： Ching-Hung KAO ,  Hsin-Ping Wu

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L27/14636 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/14689

Abstract: An image sensor comprises a substrate, a plurality of photoelectric transducer devices, an interconnect structure, at least one dielectric isolator and a back-side alignment mark. The substrate has a front-side surface and a back-side surface opposite to the front-side surface. The interconnect structure is disposed on the front-side surface. The photoelectric transducer devices are formed on the front-side surface. The dielectric isolator extends downwards into the substrate from the back-side surface in order to isolate the photoelectric transducer devices. The back-side alignment mark extends downwards into the substrate from the back-side surface and references to a front-side alignment mark previously formed on the front-side surface.

Abstract translation: 图像传感器包括基板，多个光电传感器装置，互连结构，至少一个介质隔离器和背面对准标记。 基板具有与前侧表面相对的前侧表面和后侧表面。 互连结构设置在前侧表面上。 光电传感器装置形成在前侧表面上。 介质隔离器从背面向下延伸到基板中，以隔离光电传感器装置。 后侧对准标记从后侧表面向下延伸到基板中，并且提到预先形成在前侧表面上的前侧对准标记。

公开(公告)号：US20110045626A1

公开(公告)日：2011-02-24

申请号：US12544204

申请日：2009-08-19

Applicant: Ching-Hung KAO

Inventor： Ching-Hung KAO

IPC: H01L31/18 ,  H01L31/0216

CPC classification number: H01L27/14632 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14685 ,  H01L27/14687

Abstract: A method for fabricating an optical device includes providing a semiconductor substrate having an element region and a peripheral region. The element region has an element array comprised of semiconductor elements formed therein. The peripheral region has at least a bonding pad electrically connected to the element array. A dielectric layer with an opening exposing the bonding pad is formed over the semiconductor substrate. A filter array and a planarizing layer are sequentially formed on the dielectric layer, and an organic layer is filled into the opening. An inorganic layer is formed on the planarizing layer and covers the organic layer. A portion of the inorganic layer and the organic layer are sequentially removed until the bonding pad is exposed. The organic layer protects the bonding pad from corrosion during the step removing the inorganic layer, and thus the fabrication yield is improved.

Abstract translation: 一种制造光学器件的方法包括提供具有元件区域和周边区域的半导体衬底。 元件区域具有由其中形成的半导体元件组成的元件阵列。 外围区域至少具有与元件阵列电连接的接合焊盘。 在半导体衬底上形成具有暴露焊盘的开口的电介质层。 在电介质层上依次形成滤光器阵列和平坦化层，并将有机层填充到开口内。 在平坦化层上形成无机层并覆盖有机层。 依次除去无机层和有机层的一部分，直到接合焊盘露出。 有机层在去除无机层的步骤期间保护接合焊盘免受腐蚀，从而提高制造产率。

公开(公告)号：US20130034949A1

公开(公告)日：2013-02-07

申请号：US13204072

申请日：2011-08-05

Applicant: Ching-Hung KAO

Inventor： Ching-Hung KAO

IPC: H01L21/762

CPC classification number: H01L21/308 ,  H01L21/76229

Abstract: A method of forming trench isolation with different depths of a semiconductor device is disclosed. A semiconductor substrate having a first mask layer formed thereon is first provided. A first etching process is performed with the first mask layer as an etching mask to form a shallow trench structure, followed by forming a first dielectric layer on the semiconductor substrate to fill the shallow trench structure. The first dielectric layer is then patterned to form a second mask layer which is used in a second etching process to form a deep trench structure. After that, a dielectric material is applied to fill the deep trench structure.

Abstract translation: 公开了一种形成具有不同深度的半导体器件的沟槽隔离的方法。 首先提供其上形成有第一掩模层的半导体衬底。 利用第一掩模层作为蚀刻掩模进行第一蚀刻工艺以形成浅沟槽结构，随后在半导体衬底上形成第一介电层以填充浅沟槽结构。 然后将第一介电层图案化以形成第二掩模层，其用于第二蚀刻工艺以形成深沟槽结构。 之后，施加电介质材料以填充深沟槽结构。