公开(公告)号：US08779539B2

公开(公告)日：2014-07-15

申请号：US13238076

申请日：2011-09-21

Applicant: Ching-Hung Kao ,  Hsin-Ping Wu

Inventor： Ching-Hung Kao ,  Hsin-Ping Wu

IPC: H01L31/0232 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/14689

Abstract: An image sensor comprises a substrate, a plurality of photoelectric transducer devices, an interconnect structure, at least one dielectric isolator and a back-side alignment mark. The substrate has a front-side surface and a back-side surface opposite to the front-side surface. The interconnect structure is disposed on the front-side surface. The photoelectric transducer devices are formed on the front-side surface. The dielectric isolator extends downwards into the substrate from the back-side surface in order to isolate the photoelectric transducer devices. The back-side alignment mark extends downwards into the substrate from the back-side surface and references to a front-side alignment mark previously formed on the front-side surface.

Abstract translation: 图像传感器包括基板，多个光电传感器装置，互连结构，至少一个介质隔离器和背面对准标记。 基板具有与前侧表面相对的前侧表面和后侧表面。 互连结构设置在前侧表面上。 光电传感器装置形成在前侧表面上。 介质隔离器从背面向下延伸到基板中，以隔离光电传感器装置。 后侧对准标记从后侧表面向下延伸到基板中，并且提到预先形成在前侧表面上的前侧对准标记。

公开(公告)号：US08779344B2

公开(公告)日：2014-07-15

申请号：US13547017

申请日：2012-07-11

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H04N5/335 ,  H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/14689

Abstract: An image sensor includes a substrate with a front side and a back side, the substrate having a sensor array region and a peripheral region defined thereon, a plurality of sensor device disposed in the sensor array region, a first metal layer disposed on the front sides within the peripheral region, a bonding pad disposed on the backside within the peripheral region, and at least a connecting element penetrating the substrate and substantially connect to the first metal layer and the bonding pad, wherein parts of the substrate is between the bonding pad and the first metal layer.

Abstract translation: 图像传感器包括具有前侧和背面的基板，所述基板具有传感器阵列区域和限定在其上的外围区域，设置在传感器阵列区域中的多个传感器装置，设置在前侧的第一金属层 在周边区域内，设置在周边区域的背面的接合焊盘，以及至少穿过基板的连接元件，并且基本上连接到第一金属层和接合焊盘，其中，基板的一部分在接合焊盘和 第一个金属层。

公开(公告)号：US08698216B2

公开(公告)日：2014-04-15

申请号：US13451625

申请日：2012-04-20

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L27/088 ,  H01L29/94

CPC classification number: H01L27/11534 ,  H01L21/28273 ,  H01L21/823456 ,  H01L29/4983 ,  H01L29/78

Abstract: The present disclosure provides a fabricating method of a semiconductor chip which includes the following steps. First, a substrate is provided. The substrate defines a memory unit region and a peripheral logic region. Then, a first spacer is formed around a stack structure of the memory unit region. The first space includes a first silicon oxide layer and the first silicon oxide layer directly contacts with the stack structure. After that, a silicon nitride layer is formed on both the first spacer and the peripheral logic region. Finally, the additional silicon nitride layer on the first spacer is removed but portions of the additional silicon nitride layer around gate structures in the peripheral logic region are remained.

Abstract translation: 本公开提供了一种半导体芯片的制造方法，包括以下步骤。 首先，提供基板。 衬底限定存储器单元区域和外围逻辑区域。 然后，围绕存储单元区域的堆叠结构形成第一间隔物。 第一空间包括第一氧化硅层，并且第一氧化硅层与堆叠结构直接接触。 之后，在第一间隔物和周边逻辑区域上形成氮化硅层。 最后，去除第一间隔物上的另外的氮化硅层，但是剩余外围逻辑区域中的栅极结构周围的附加氮化硅层的部分。

公开(公告)号：US08643101B2

公开(公告)日：2014-02-04

申请号：US13090338

申请日：2011-04-20

Applicant: Ching-Hung Kao ,  Sheng-Hsiong Yang

Inventor： Ching-Hung Kao ,  Sheng-Hsiong Yang

IPC: H01L29/788

CPC classification number: H01L29/66689 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7816

Abstract: A high voltage metal oxide semiconductor device with low on-state resistance is provided. A multi-segment isolation structure is arranged under a gate structure and beside a drift region for blocking the current from directly entering the drift region. Due to the multi-segment isolation structure, the path length from the body region to the drift region is increased. Consequently, as the breakdown voltage applied to the gate structure is increased, the on-state resistance is reduced.

Abstract translation: 提供具有低导通电阻的高电压金属氧化物半导体器件。 多段隔离结构被布置在栅极结构之下并且在漂移区旁边，用于阻止电流直接进入漂移区。 由于多段隔离结构，从身体区域到漂移区域的路径长度增加。 因此，随着施加到栅极结构的击穿电压增加，导通电阻降低。

公开(公告)号：US20140015083A1

公开(公告)日：2014-01-16

申请号：US13547017

申请日：2012-07-11

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L27/14636 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/14689

Abstract: An image sensor includes a substrate with a front side and a back side, the substrate having a sensor array region and a peripheral region defined thereon, a plurality of sensor device disposed in the sensor array region, a first metal layer disposed on the front sides within the peripheral region, a bonding pad disposed on the backside within the peripheral region, and at least a connecting element penetrating the substrate and substantially connect to the first metal layer and the bonding pad, wherein parts of the substrate is between the bonding pad and the first metal layer.

Abstract translation: 图像传感器包括具有前侧和背面的基板，所述基板具有传感器阵列区域和限定在其上的外围区域，设置在传感器阵列区域中的多个传感器装置，设置在前侧的第一金属层 在周边区域内，设置在周边区域的背面的接合焊盘，以及至少穿过基板的连接元件，并且基本上连接到第一金属层和接合焊盘，其中，基板的一部分在接合焊盘和 第一个金属层。

公开(公告)号：US20130034949A1

公开(公告)日：2013-02-07

申请号：US13204072

申请日：2011-08-05

Applicant: Ching-Hung KAO

Inventor： Ching-Hung KAO

IPC: H01L21/762

CPC classification number: H01L21/308 ,  H01L21/76229

Abstract: A method of forming trench isolation with different depths of a semiconductor device is disclosed. A semiconductor substrate having a first mask layer formed thereon is first provided. A first etching process is performed with the first mask layer as an etching mask to form a shallow trench structure, followed by forming a first dielectric layer on the semiconductor substrate to fill the shallow trench structure. The first dielectric layer is then patterned to form a second mask layer which is used in a second etching process to form a deep trench structure. After that, a dielectric material is applied to fill the deep trench structure.

Abstract translation: 公开了一种形成具有不同深度的半导体器件的沟槽隔离的方法。 首先提供其上形成有第一掩模层的半导体衬底。 利用第一掩模层作为蚀刻掩模进行第一蚀刻工艺以形成浅沟槽结构，随后在半导体衬底上形成第一介电层以填充浅沟槽结构。 然后将第一介电层图案化以形成第二掩模层，其用于第二蚀刻工艺以形成深沟槽结构。 之后，施加电介质材料以填充深沟槽结构。

公开(公告)号：US08334189B2

公开(公告)日：2012-12-18

申请号：US13011936

申请日：2011-01-24

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L21/76

CPC classification number: H01L21/76229

Abstract: A method for forming trench isolation on a substrate includes providing a substrate having thereon a pad layer and a hard mask; forming a first shallow trench in a first area and a second trench in a second area on the substrate; forming a resist layer covering the first area while exposing the second area; etching the second shallow trench to form a deep trench; forming oxide liner within the first shallow trench and the deep trench; and filling the shallow trench and the deep trench with an oxide layer.

Abstract translation: 在衬底上形成沟槽隔离的方法包括提供其上具有衬垫层和硬掩模的衬底; 在第一区域中形成第一浅沟槽和在衬底上的第二区域中形成第二沟槽; 在暴露所述第二区域的同时形成覆盖所述第一区域的抗蚀剂层; 蚀刻第二浅沟槽以形成深沟槽; 在第一浅沟槽和深沟槽内形成氧化物衬垫; 并用氧化物层填充浅沟槽和深沟槽。

公开(公告)号：US08039286B2

公开(公告)日：2011-10-18

申请号：US12544204

申请日：2009-08-19

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L21/00

CPC classification number: H01L27/14632 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14685 ,  H01L27/14687

Abstract: A method for fabricating an optical device includes providing a semiconductor substrate having an element region and a peripheral region. The element region has an element array comprised of semiconductor elements formed therein. The peripheral region has at least a bonding pad electrically connected to the element array. A dielectric layer with an opening exposing the bonding pad is formed over the semiconductor substrate. A filter array and a planarizing layer are sequentially formed on the dielectric layer, and an organic layer is filled into the opening. An inorganic layer is formed on the planarizing layer and covers the organic layer. A portion of the inorganic layer and the organic layer are sequentially removed until the bonding pad is exposed. The organic layer protects the bonding pad from corrosion during the step removing the inorganic layer, and thus the fabrication yield is improved.

Abstract translation: 一种制造光学器件的方法包括提供具有元件区域和周边区域的半导体衬底。 元件区域具有由其中形成的半导体元件组成的元件阵列。 外围区域至少具有与元件阵列电连接的接合焊盘。 在半导体衬底上形成具有暴露焊盘的开口的电介质层。 在电介质层上依次形成滤光器阵列和平坦化层，并将有机层填充到开口内。 在平坦化层上形成无机层并覆盖有机层。 依次除去无机层和有机层的一部分，直到接合焊盘露出。 有机层在去除无机层的步骤期间保护接合焊盘免受腐蚀，从而提高制造产率。

公开(公告)号：US07741662B2

公开(公告)日：2010-06-22

申请号：US12252343

申请日：2008-10-15

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L29/72

CPC classification number: H01L29/7835 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7816

Abstract: An ultra high voltage MOS transistor device includes a substrate; a source region formed in the substrate; a first doping region formed in the substrate and bordering upon the source region; a first ion well encompassing the source region and the first doping region; a gate oxide layer formed on the source region and on the first ion well; a field oxide layer connected with the gate oxide layer and formed on a semiconductor region; a dielectric layer stacked on the field oxide layer; a drain region formed at one side of the field oxide layer and being spaced apart from the source region; a second ion well encompassing the drain region; and a gate disposed on the gate oxide layer and laterally extending to the field oxide layer and onto the dielectric layer.

Abstract translation: 超高压MOS晶体管器件包括：衬底; 形成在所述基板中的源极区域; 形成在所述衬底中并与所述源极区域接壤的第一掺杂区域; 包括所述源区和所述第一掺杂区的第一离子阱; 形成在所述源极区域和所述第一离子阱上的栅极氧化物层; 与所述栅极氧化层连接并形成在半导体区域上的场氧化物层; 堆叠在场氧化物层上的电介质层; 漏极区，形成在所述场氧化物层的一侧并且与所述源极区间隔开; 包围漏区的第二离子阱; 以及设置在栅极氧化物层上并横向延伸到场氧化物层和介电层上的栅极。

公开(公告)号：US07535063B2

公开(公告)日：2009-05-19

申请号：US11160518

申请日：2005-06-28

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L29/94

CPC classification number: H01L27/0266

Abstract: An electrostatic discharge (ESD) protective device structure. The ESD protection device includes: at least a first conductive type metal-oxide semiconductor (MOS), in which the drain and source of the first conductive type MOS are electrically connected to a first power terminal and a second power terminal separately; at least a second conductive type diffusion region; and at least a dummy gate disposed between the first conductive type MOS and the second conductive type diffusion region, wherein the gate length of the dummy gate is less than the gate length of the first conductive type MOS gate, such that the junction between the second conductive type diffusion region and the drain of the first conductive type MOS have a low breakdown voltage.

Abstract translation: 静电放电（ESD）保护装置结构。 ESD保护装置包括：至少第一导电型金属氧化物半导体（MOS），其中第一导电型MOS的漏极和源极分别电连接到第一电力端子和第二电力端子; 至少第二导电型扩散区域; 并且至少设置在所述第一导电型MOS与所述第二导电型扩散区之间的虚拟栅极，其中所述伪栅极的栅极长度小于所述第一导电型MOS栅极的栅极长度，使得所述第二 导电型扩散区域和第一导电型MOS的漏极具有低击穿电压。