公开(公告)号：US20130189825A1

公开(公告)日：2013-07-25

申请号：US13555356

申请日：2012-07-23

Applicant: Yannick LE TIEC ,  Laurent GRENOUILLET ,  Maud VINET

Inventor： Yannick LE TIEC ,  Laurent GRENOUILLET ,  Maud VINET

IPC: H01L21/76

CPC classification number: H01L21/76 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76237 ,  H01L21/76283

Abstract: A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the support layer and a semiconductive layer resting on said insulating layer, the method comprising steps of: a) localised doping of a given portion of said insulating layer through an opening in a masking layer resting on the fine semiconductive layer, b) selective removal of said given doped area at the bottom of said opening.

Abstract translation: 一种在包括由半导体支撑层形成的绝缘体上半导体基板的基板和搁置在所述绝缘层上的绝缘层和置于所述绝缘层上的半导电层的器件中制造一个或多个沟槽的方法，所述方法包括以下步骤： ：a）通过位于精细半导体层上的掩模层中的开口局部掺杂所述绝缘层的给定部分，b）选择性地去除所述开口底部的所述给定掺杂区域。

公开(公告)号：US20120088352A1

公开(公告)日：2012-04-12

申请号：US13273982

申请日：2011-10-14

Applicant: Rémi Beneyton ,  Hubert Moriceau ,  Frank Fournel ,  François Rieutord ,  Yannick Le Tiec

Inventor： Rémi Beneyton ,  Hubert Moriceau ,  Frank Fournel ,  François Rieutord ,  Yannick Le Tiec

IPC: H01L21/762

CPC classification number: C09J5/06

Abstract: The invention relates to a process for producing a bond between a first and a second substrate. The process includes preparing surfaces of the substrates to be assembled, and attaching the surfaces to form an assembly of these two surfaces, by direct molecular bonding. The assembly is then heat treated, which includes maintaining the temperature within the range of 50° C. to 100° C. for at least one hour.

Abstract translation: 本发明涉及一种用于在第一和第二基底之间产生粘结的方法。 该方法包括制备要组装的基底的表面，并且通过直接分子键合来附着表面以形成这两个表面的组合。 然后对组件进行热处理，其包括将温度保持在50℃至100℃的范围内至少1小时。

公开(公告)号：US20150294903A1

公开(公告)日：2015-10-15

申请号：US14425891

申请日：2012-09-05

Applicant: Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet ,  Romain Wacquez

Inventor： Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet ,  Romain Wacquez

IPC: H01L21/762 ,  H01L21/306 ,  H01L21/265 ,  H01L21/84

CPC classification number: H01L21/76283 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84

Abstract: A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

Abstract translation: 一种在包括第一半导体层，电介质层和第二半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过所述第一半导体层，所述电介质层和所述第一半导体层的厚度的一部分蚀刻沟槽 从而在所述第一半导体层中限定所述微电子器件的一个有源区域，在所述沟槽的一个或多个侧壁中的离子注入，在所述第二半导体层的水平处，修改所述晶体学性质和/或所述第二半导体层， 注入半导体的化学性质，蚀刻注入的半导体，使得沟槽的至少一部分在有源区的一部分下方延伸，用电介质材料填充沟槽，形成围绕有源区的隔离沟槽，并且包括 在有源区域的一部分下延伸的部分。

公开(公告)号：US20120187489A1

公开(公告)日：2012-07-26

申请号：US13356975

申请日：2012-01-24

Applicant: Laurent GRENOUILLET ,  Yannick LE TIEC ,  Nicolas POSSEME ,  Maud VINET

Inventor： Laurent GRENOUILLET ,  Yannick LE TIEC ,  Nicolas POSSEME ,  Maud VINET

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/78618 ,  H01L21/26586 ,  H01L29/66772 ,  H01L29/78696

Abstract: The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.

Abstract translation: 场效应器件包括牺牲栅极电极，其侧壁由形成在半导体材料膜上的横向间隔件覆盖。 源极/漏极形成在半导体材料膜中并且布置在栅电极的每一侧上。 扩散阻挡元件通过由牺牲栅极留下的空隙注入，以便在侧向间隔物下方形成修改的扩散区域。 改性扩散区域是与源/漏电极相比掺杂杂质的迁移率降低的区域。

公开(公告)号：US08994142B2

公开(公告)日：2015-03-31

申请号：US13439356

申请日：2012-04-04

Applicant: Maud Vinet ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Posseme

Inventor： Maud Vinet ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Posseme

IPC: H01L21/70 ,  H01L27/12 ,  H01L21/44 ,  H01L29/786 ,  H01L21/74 ,  H01L21/762

CPC classification number: H01L29/78648 ,  H01L21/743 ,  H01L21/76283

Abstract: The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode.

Abstract translation: 场效应晶体管包括依次包括导电支撑衬底，电绝缘层和半导体材料层的衬底。 对置电极形成在支撑基板的面向半导体材料层的第一部分中。 绝缘图案围绕半导体材料层以描绘第一有源区域并且其部分地穿透到支撑层中以描绘第一部分。 导电接触通过绝缘图案从与对电极接触的第一侧表面穿过第二表面。 触点电连接到对电极。

公开(公告)号：US08530331B2

公开(公告)日：2013-09-10

申请号：US13273982

申请日：2011-10-14

Applicant: Remi Beneyton ,  Hubert Moriceau ,  Frank Fournel ,  Francois Rieutord ,  Yannick Le Tiec

Inventor： Remi Beneyton ,  Hubert Moriceau ,  Frank Fournel ,  Francois Rieutord ,  Yannick Le Tiec

IPC: H01L21/30

CPC classification number: C09J5/06

Abstract: The invention relates to a process for producing a bond between a first and a second substrate. The process includes preparing surfaces of the substrates to be assembled, and attaching the surfaces to form an assembly of these two surfaces, by direct molecular bonding. The assembly is then heat treated, which includes maintaining the temperature within the range of 50° C. to 100° C. for at least one hour.

Abstract translation: 本发明涉及一种用于在第一和第二基底之间产生粘结的方法。 该方法包括制备要组装的基底的表面，并且通过直接分子键合来附着表面以形成这两个表面的组合。 然后对组件进行热处理，其包括将温度保持在50℃至100℃的范围内至少1小时。

公开(公告)号：US20110284870A1

公开(公告)日：2011-11-24

申请号：US13057239

申请日：2009-08-13

Applicant: Yannick Le Tiec ,  Francois Andrieu

Inventor： Yannick Le Tiec ,  Francois Andrieu

IPC: H01L29/02 ,  H01L29/06 ,  H01L21/18

CPC classification number: H01L29/1608 ,  H01L21/76254

Abstract: A method for making a semiconducting structure, including: a) forming, on a surface of a final semiconductor substrate, a semiconducting layer, doped with elements from columns III and V of the Periodic Table so as to form a ground plane, b) forming a dielectric layer, c) then assembling, by direct adhesion of the source substrate, on the final substrate, the layer forming the ground plane between the final substrate and the source substrate, the dielectric layer being between the source substrate and the ground plane, d) then thinning the source substrate, leaving, on the surface of the semiconductor structure, a film made from a semiconducting material.

Abstract translation: 一种制造半导体结构的方法，包括：a）在最终半导体衬底的表面上形成半导体层，掺杂元素周期表的第三和第五列的元素以形成接地面; b）形成 电介质层，c）然后通过源衬底的直接粘附在最终衬底上组装在最终衬底和源衬底之间形成接地平面的层，介电层位于源极衬底和接地平面之间， d）然后使源衬底变薄，在半导体结构的表面上留下由半导体材料制成的膜。

公开(公告)号：US09437474B2

公开(公告)日：2016-09-06

申请号：US14425891

申请日：2012-09-05

Applicant: Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet ,  Romain Wacquez

Inventor： Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet ,  Romain Wacquez

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/265 ,  H01L21/306

CPC classification number: H01L21/76283 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84

Abstract: A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

Abstract translation: 一种在包括第一半导体层，电介质层和第二半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过所述第一半导体层，所述电介质层和所述第一半导体层的厚度的一部分蚀刻沟槽 从而在所述第一半导体层中限定所述微电子器件的一个有源区域，在所述沟槽的一个或多个侧壁中的离子注入，在所述第二半导体层的水平处，修改所述晶体学性质和/或所述第二半导体层， 注入半导体的化学性质，蚀刻注入的半导体，使得沟槽的至少一部分在有源区的一部分下方延伸，用电介质材料填充沟槽，形成围绕有源区的隔离沟槽，并且包括 在有源区域的一部分下延伸的部分。

公开(公告)号：US08603872B2

公开(公告)日：2013-12-10

申请号：US13356975

申请日：2012-01-24

Applicant: Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Posseme ,  Maud Vinet

Inventor： Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Posseme ,  Maud Vinet

IPC: H01L21/336

CPC classification number: H01L29/78618 ,  H01L21/26586 ,  H01L29/66772 ,  H01L29/78696

Abstract: The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.

Abstract translation: 场效应器件包括牺牲栅极电极，其侧壁由形成在半导体材料膜上的横向间隔件覆盖。 源极/漏极形成在半导体材料膜中并且布置在栅电极的每一侧上。 扩散阻挡元件通过由牺牲栅极留下的空隙注入，以便在侧向间隔物下方形成修改的扩散区域。 改性扩散区域是与源/漏电极相比掺杂杂质的迁移率降低的区域。

公开(公告)号：US08501588B2

公开(公告)日：2013-08-06

申请号：US13057239

申请日：2009-08-13

Applicant: Yannick Le Tiec ,  Francois Andrieu

Inventor： Yannick Le Tiec ,  Francois Andrieu

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/76

CPC classification number: H01L29/1608 ,  H01L21/76254

Abstract: A method for making a semiconducting structure, including: a) forming, on a surface of a final semiconductor substrate, a semiconducting layer, doped with elements from columns III and V of the Periodic Table so as to form a ground plane, b) forming a dielectric layer, c) then assembling, by direct adhesion of the source substrate, on the final substrate, the layer forming the ground plane between the final substrate and the source substrate, the dielectric layer being between the source substrate and the ground plane, d) then thinning the source substrate, leaving, on the surface of the semiconductor structure, a film made from a semiconducting material.

Abstract translation: 一种制造半导体结构的方法，包括：a）在最终半导体衬底的表面上形成半导体层，掺杂元素周期表的第三和第五列的元素以形成接地面; b）形成 电介质层，c）然后通过源衬底的直接粘附在最终衬底上组装在最终衬底和源衬底之间形成接地平面的层，介电层位于源极衬底和接地平面之间， d）然后使源衬底变薄，在半导体结构的表面上留下由半导体材料制成的膜。