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    VERTICAL PACKAGING FOR ULTRASOUND-ON-A-CHIP AND RELATED METHODS
    111.
    发明申请
    VERTICAL PACKAGING FOR ULTRASOUND-ON-A-CHIP AND RELATED METHODS 审中-公开

    公开(公告)号：US20190336103A1

    公开(公告)日：2019-11-07

    申请号：US16401249

    申请日：2019-05-02

    Applicant: Butterfly Network, Inc.

    Inventor： Keith G. Fife ,  Jianwei Liu

    IPC: A61B8/00 ,  H01L41/113 ,  H01L41/293

    Abstract: Vertical packaging configurations for ultrasound chips are described. Vertical packaging may involve use of integrated interconnects other than wires for wire bonding. Examples of such integrated interconnects include edge-contact vias, through silicon vias and conductive pillars. Edge-contact vias are vias defined in a trench formed in the ultrasound chip. Multiple vias may be provided for each trench, thus increasing the density of vias. Such vias enable electric access to the ultrasound transducers. Through silicon vias are formed through the silicon handle and provide access from the bottom surface of the ultrasound chip. Conductive pillars, including copper pillars, are disposed around the perimeter of an ultrasound chip and provide access to the ultrasound transducers from the top surface of the chip. Use of these types of packaging techniques can enable a substantial reduction in the dimensions of an ultrasound device.

    ULTRASOUND TRANSDUCER DEVICES AND METHODS FOR FABRICATING ULTRASOUND TRANSDUCER DEVICES
    113.
    发明申请
    ULTRASOUND TRANSDUCER DEVICES AND METHODS FOR FABRICATING ULTRASOUND TRANSDUCER DEVICES 审中-公开

    公开(公告)号：US20190275561A1

    公开(公告)日：2019-09-12

    申请号：US16296476

    申请日：2019-03-08

    Applicant: Butterfly Network, Inc.

    Inventor： Keith G. Fife ,  Jianwei Liu

    IPC: B06B1/02

    Abstract: Aspects of the technology described herein relate to ultrasound transducer devices including capacitive micromachined ultrasonic transducers (CMUTs) and methods for forming CMUTs in ultrasound transducer devices. Some embodiments include forming a cavity of a CMUT by forming a first layer of insulating material on a first substrate, forming a second layer of insulating material on the first layer of insulating material, and then etching a cavity in the second insulating material. A second substrate may be bonded to the first substrate to seal the cavity. The first layer of insulating material may include, for example, aluminum oxide. The first substrate may include integrated circuitry. Some embodiments include forming through-silicon vias (TSVs) in the first substrate prior to forming the first and second insulating layers (TSV-Middle process) or subsequent to bonding the first and second substrates (TSV-Last process).

    ULTRASOUND APPARATUSES AND METHODS FOR FABRICATING ULTRASOUND DEVICES
    114.
    发明申请
    ULTRASOUND APPARATUSES AND METHODS FOR FABRICATING ULTRASOUND DEVICES 审中-公开

    公开(公告)号：US20190261955A1

    公开(公告)日：2019-08-29

    申请号：US16404672

    申请日：2019-05-06

    Applicant: Butterfly Network, Inc.

    Inventor： Kailiang Chen ,  Nevada J. Sanchez ,  Susan A. Alie ,  Tyler S. Ralston ,  Jonathan M. Rothberg ,  Keith G. Fife ,  Joseph Lutsky

    IPC: A61B8/08 ,  H04B11/00

    Abstract: Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.

    ULTRASOUND APPARATUSES AND METHODS FOR FABRICATING ULTRASOUND DEVICES
    115.
    发明申请
    ULTRASOUND APPARATUSES AND METHODS FOR FABRICATING ULTRASOUND DEVICES 审中-公开

    公开(公告)号：US20190261954A1

    公开(公告)日：2019-08-29

    申请号：US16404665

    申请日：2019-05-06

    Applicant: Butterfly Network, Inc.

    Inventor： Kailiang Chen ,  Nevada J. Sanchez ,  Susan A. Alie ,  Tyler S. Ralston ,  Jonathan M. Rothberg ,  Keith G. Fife ,  Joseph Lutsky

    IPC: A61B8/08 ,  H04B11/00

    Abstract: Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.

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