公开(公告)号：US08861149B2

公开(公告)日：2014-10-14

申请号：US12986450

申请日：2011-01-07

申请人： Ming-Hsien Tsai

发明人： Ming-Hsien Tsai

IPC分类号： H02H9/04 ,  H03F1/52 ,  H01L27/02 ,  H03F3/193 ,  H03F1/22

CPC分类号： H01L27/0255 ,  H01L27/0288 ,  H02H9/046 ,  H03F1/223 ,  H03F1/52 ,  H03F3/193 ,  H03F2200/294 ,  H03F2200/441 ,  H03F2200/444 ,  Y10T29/49117

摘要： The present disclosure provides a circuit that has an electrostatic discharge (ESD) protection device and a protected circuit in communication with the ESD protection device. The ESD protection device has a first inductor between a signal input terminal and a complimentary power line. The first inductor has a length less than ¼ of a normal operating wavelength of the protected circuit. The ESD protection device also has a first capacitor between the signal input terminal and the protected circuit.

摘要翻译： 本公开提供一种具有静电放电（ESD）保护装置和与ESD保护装置通信的受保护电路的电路。 ESD保护装置在信号输入端和互补电源线之间具有第一电感器。 第一电感器的长度小于受保护电路的正常工作波长的1/4。 ESD保护器件还在信号输入端子和保护电路之间具有第一电容器。

公开(公告)号：US08786367B2

公开(公告)日：2014-07-22

申请号：US13523851

申请日：2012-06-14

申请人： Yung-Ming Lee ,  Tzu-Fei Han

发明人： Yung-Ming Lee ,  Tzu-Fei Han

IPC分类号： H03G3/10 ,  H03F1/26 ,  H03G11/00

CPC分类号： H03F1/26 ,  H03F2200/03 ,  H03F2200/411 ,  H03F2200/441 ,  H03G11/002

摘要： A voltage clamping module is disposed at an output terminal of a gain amplifying module, so that a voltage level of an amplifying signal outputted by the gain amplifying module can be clamped within a predetermined range. The voltage clamping module includes an upper bound voltage clamping module, which is utilized for limiting the voltage level of the amplifying signal to be lower than an upper bound voltage level, and a lower bound voltage clamping module, which is utilized for limiting the voltage level of the amplifying signal to be higher than a lower bound voltage level.

摘要翻译： 电压钳位模块设置在增益放大模块的输出端，使得增益放大模块输出的放大信号的电压电平可以钳位在预定范围内。 电压钳位模块包括用于将放大信号的电压电平限制为低于上限电压电平的上限电压钳位模块和用于限制电压电平的下限钳位模块 的放大信号高于下限电压电平。

公开(公告)号：US20140104003A1

公开(公告)日：2014-04-17

申请号：US14052244

申请日：2013-10-11

申请人： Lei Huang ,  Hongtao LV ,  Yangfang Li

发明人： Lei Huang ,  Hongtao LV ,  Yangfang Li

IPC分类号： H03F1/52

CPC分类号： H03F1/523 ,  H03F3/45183 ,  H03F2200/441

摘要： The disclosure provides an operational amplifier circuit, in which a power supply of an amplifying circuit is coupled to a first voltage clamping circuit, and the first voltage clamping circuit clamps a supply voltage of the amplifying circuit when the supply voltage exceeds a normal-operation allowable voltage of the amplifying circuit. The disclosure also provides a method for implementing the operational amplifier circuit. According to the disclosure, the operational circuit may be avoided from subject to an excessive supply voltage, which may damage devices in the amplifying circuit of the operational amplifier.

摘要翻译： 本公开提供了一种运算放大器电路，其中放大电路的电源耦合到第一钳位电路，并且当电源电压超过正常工作允许值时，第一钳位电路钳位放大电路的电源电压 放大电路的电压。 本公开还提供了一种用于实现运算放大器电路的方法。 根据本公开，可以避免操作电路遭受过大的电源电压，这可能损坏运算放大器的放大电路中的装置。

公开(公告)号：US08487687B2

公开(公告)日：2013-07-16

申请号：US12750671

申请日：2010-03-30

申请人： Xie-Ren Hsu ,  Ji-Ting Chen

发明人： Xie-Ren Hsu ,  Ji-Ting Chen

IPC分类号： H03K5/08 ,  H03F3/45

CPC分类号： H03K19/018514 ,  G09G3/20 ,  G09G2310/0275 ,  G09G2310/0291 ,  H03F2200/441 ,  H03F2203/45136 ,  H03K5/08 ,  H03K5/2481 ,  H03K19/00361

摘要： An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.

摘要翻译： 用于避免电压过冲的输出缓冲电路包括输入级，输出偏置电路，输出级，钳位电路和控制单元。 输入级包括用于接收输入电压的正输入端子和负输入端子。 输入级根据输入电压产生电流信号。 输出偏置电路耦合到输入级，用于根据电流信号产生动态偏置。 输出级耦合到输入级和输出偏置电路，包括反向耦合到正输入端的输出端和耦合到输出偏置电路和输出端的至少一个输出晶体管，用于提供驱动 根据动态偏置电流到输出端产生输出电压。

公开(公告)号：US08213142B2

公开(公告)日：2012-07-03

申请号：US12260901

申请日：2008-10-29

申请人： Eugene R. Worley

发明人： Eugene R. Worley

IPC分类号： H02H9/00 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06

CPC分类号： H03F1/523 ,  H01L27/0255 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/294 ,  H03F2200/441 ,  H03F2200/444 ,  H03F2200/492 ,  H03F2203/45314 ,  H03F2203/45386 ,  H03F2203/45568

摘要： An amplifier (e.g., an LNA) with improved ESD protection circuitry is described. In one exemplary design, the amplifier includes a transistor, an inductor, and a clamp circuit. The transistor has a gate coupled to a pad and provides signal amplification for the amplifier. The inductor is coupled to a source of the transistor and provides source degeneration for the transistor. The clamp circuit is coupled between the gate and source of the transistor and provides ESD protection for the transistor. The clamp circuit may include at least one diode coupled between the gate and source of the transistor. The clamp circuit conducts current through the inductor to generate a voltage drop across the inductor when a large voltage pulse is applied to the pad. The gate-to-source voltage (Vgs) of the transistor is reduced by the voltage drop across the inductor, which may improve the reliability of the transistor.

摘要翻译： 描述了具有改进的ESD保护电路的放大器（例如，LNA）。 在一个示例性设计中，放大器包括晶体管，电感器和钳位电路。 晶体管具有耦合到焊盘并且为放大器提供信号放大的栅极。 电感器耦合到晶体管的源极，并为晶体管提供源极退化。 钳位电路耦合在晶体管的栅极和源极之间，并为晶体管提供ESD保护。 钳位电路可以包括耦合在晶体管的栅极和源极之间的至少一个二极管。 当对焊盘施加大的电压脉冲时，钳位电路通过电感器传导电流，以在电感器两端产生电压降。 晶体管的栅极 - 源极电压（Vgs）被电感器两端的电压降降低，这可能会提高晶体管的可靠性。

公开(公告)号：US08169761B2

公开(公告)日：2012-05-01

申请号：US12400799

申请日：2009-03-10

申请人： Chih-Ting Yeh ,  Yung-Chih Liang ,  Shih-Hung Chen

发明人： Chih-Ting Yeh ,  Yung-Chih Liang ,  Shih-Hung Chen

IPC分类号： H02H9/00

CPC分类号： H03F1/523 ,  H01L27/0266 ,  H03F2200/441

摘要： An ESD clamp circuit applied to a power amplifier is provided. The ESD clamp circuit includes a first line, a second line, a first circuit, a second circuit, an ESD detecting unit, a buffer unit, and an ESD clamp unit. The first line is coupled to the output terminal of the power amplifier. The first circuit is coupled to the first line. The second circuit is coupled to the first circuit. The ESD detecting unit is coupled to the first circuit and the second line. The buffer unit is coupled to the second circuit, the second line and the ESD detecting unit. The ESD clamp unit is coupled to the buffer unit, the first line and the second line. Therefore, at normal operation mode, the problem of signal loss caused by the leakage current of ESD clamp circuit can be avoided.

摘要翻译： 提供了应用于功率放大器的ESD钳位电路。 ESD钳位电路包括第一线，第二线，第一电路，第二电路，ESD检测单元，缓冲单元和ESD钳位单元。 第一行耦合到功率放大器的输出端。 第一电路耦合到第一线。 第二电路耦合到第一电路。 ESD检测单元耦合到第一电路和第二线。 缓冲单元耦合到第二电路，第二线路和ESD检测单元。 ESD钳位单元耦合到缓冲单元，第一线和第二线。 因此，在正常工作模式下，可以避免由ESD钳位电路的漏电流引起的信号损失问题。

公开(公告)号：US07881030B1

公开(公告)日：2011-02-01

申请号：US12168179

申请日：2008-07-07

申请人： Jason Yuxin Li ,  Walter A. Wohlmuth ,  Swaminathan Muthukrishnan ,  Christian Rye Iversen ,  Nathaniel Peachey

发明人： Jason Yuxin Li ,  Walter A. Wohlmuth ,  Swaminathan Muthukrishnan ,  Christian Rye Iversen ,  Nathaniel Peachey

IPC分类号： H02H3/22

CPC分类号： H03F1/52 ,  H01Q1/50 ,  H03F2200/441

摘要： The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance, a drain-to-gate resistance, or both of the FET element, and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element and a resistive element. Therefore, the single FET element ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

摘要翻译： 本发明涉及用于保护其它电路免受高电压ESD事件的静电放电（ESD）钳位电路。 ESD钳位电路可以包括作为钳位元件的场效应晶体管（FET）元件，其通过使用漏极到栅极电容，漏极到栅极电阻或者FET元件的两者以及电阻 元件作为分压器来分压ESD电压以提供FET元件的触发栅极电压。 在其最简单的实施例中，ESD钳位电路仅包括FET元件和电阻元件。 因此，与其他ESD保护电路相比，单个FET元件ESD钳位电路可能较小。 ESD钳位电路的简单性可以使寄生电容最小化，从而在宽频率范围内最大化ESD钳位电路的线性度。

公开(公告)号：US20100149703A1

公开(公告)日：2010-06-17

申请号：US12400799

申请日：2009-03-10

申请人： Chih-Ting Yeh ,  Yung-Chih Liang ,  Shih-Hung Chen

发明人： Chih-Ting Yeh ,  Yung-Chih Liang ,  Shih-Hung Chen

IPC分类号： H02H9/04

CPC分类号： H03F1/523 ,  H01L27/0266 ,  H03F2200/441

摘要： An ESD clamp circuit applied to a power amplifier is provided. The ESD clamp circuit includes a first line, a second line, a first circuit, a second circuit, an ESD detecting unit, a buffer unit, and an ESD clamp unit. The first line is coupled to the output terminal of the power amplifier. The first circuit is coupled to the first line. The second circuit is coupled to the first circuit. The ESD detecting unit is coupled to the first circuit and the second line. The buffer unit is coupled to the second circuit, the second line and the ESD detecting unit. The ESD clamp unit is coupled to the buffer unit, the first line and the second line. Therefore, at normal operation mode, the problem of signal loss caused by the leakage current of ESD clamp circuit can be avoided.

摘要翻译： 提供了应用于功率放大器的ESD钳位电路。 ESD钳位电路包括第一线，第二线，第一电路，第二电路，ESD检测单元，缓冲单元和ESD钳位单元。 第一行耦合到功率放大器的输出端。 第一电路耦合到第一线。 第二电路耦合到第一电路。 ESD检测单元耦合到第一电路和第二线。 缓冲单元耦合到第二电路，第二线路和ESD检测单元。 ESD钳位单元耦合到缓冲单元，第一线和第二线。 因此，在正常工作模式下，可以避免由ESD钳位电路的漏电流引起的信号损失问题。

公开(公告)号：US20100073064A1

公开(公告)日：2010-03-25

申请号：US12234046

申请日：2008-09-19

申请人： William F. Ellersick

发明人： William F. Ellersick

IPC分类号： H03L5/00

CPC分类号： H03F3/45188 ,  H03F1/523 ,  H03F3/45677 ,  H03F2200/426 ,  H03F2200/441 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/462 ,  H03F2200/66 ,  H03F2203/45186 ,  H03F2203/45354 ,  H03F2203/45636 ,  H03F2203/45641 ,  H03F2203/45674 ,  H03G11/002 ,  H03G11/02

摘要： An active over-voltage clamp system includes at least one over-voltage detector that is responsive to an input voltage and provides a first current. The system also includes a replica over-voltage circuit that provides a second current, and circuitry subtracting the second current from the first current to produce a difference current. The system further includes a differential clamp activated in response to the difference current. The differential clamp prevents the input voltage from increasing beyond a target voltage.

摘要翻译： 有源过电压钳位系统包括至少一个过电压检测器，其响应输入电压并提供第一电流。 该系统还包括提供第二电流的复制过电压电路，以及从第一电流减去第二电流以产生差电流的电路。 该系统还包括响应于差动电流而被激活的差分钳位。 差分钳位器可防止输入电压超出目标电压。

公开(公告)号：US20080186102A1

公开(公告)日：2008-08-07

申请号：US11671124

申请日：2007-02-05

申请人： Moshe Gerstenhaber ,  Padraig Cooney

发明人： Moshe Gerstenhaber ,  Padraig Cooney

IPC分类号： H03F1/52

CPC分类号： H03F3/45475 ,  H03F1/523 ,  H03F2200/261 ,  H03F2200/441 ,  H03F2203/45138

摘要： An amplifier system includes an instrumentation amplifier arrangement being designed to amplify the difference between two voltage inputs with a defined gain, and to produce a single-ended output referenced to a known reference point. A front end circuit is coupled to the instrumentation amplifier. The front end circuit is configured to include a current clamp to actively limit the current in a gain resistor of the instrumentation amplifier to prevent input currents flowing when the instrumentation amplifier is over-driven.

摘要翻译： 放大器系统包括仪表放大器装置，其被设计成以确定的增益来放大两个电压输入之间的差异，并且产生参考已知参考点的单端输出。 前端电路耦合到仪表放大器。 前端电路被配置为包括电流钳，以主动地限制仪器放大器的增益电阻器中的电流，以防止当仪表放大器过驱动时输入电流流动。