公开(公告)号：US07881030B1

公开(公告)日：2011-02-01

申请号：US12168179

申请日：2008-07-07

申请人： Jason Yuxin Li ,  Walter A. Wohlmuth ,  Swaminathan Muthukrishnan ,  Christian Rye Iversen ,  Nathaniel Peachey

发明人： Jason Yuxin Li ,  Walter A. Wohlmuth ,  Swaminathan Muthukrishnan ,  Christian Rye Iversen ,  Nathaniel Peachey

IPC分类号： H02H3/22

CPC分类号： H03F1/52 ,  H01Q1/50 ,  H03F2200/441

摘要： The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance, a drain-to-gate resistance, or both of the FET element, and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element and a resistive element. Therefore, the single FET element ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

摘要翻译： 本发明涉及用于保护其它电路免受高电压ESD事件的静电放电（ESD）钳位电路。 ESD钳位电路可以包括作为钳位元件的场效应晶体管（FET）元件，其通过使用漏极到栅极电容，漏极到栅极电阻或者FET元件的两者以及电阻 元件作为分压器来分压ESD电压以提供FET元件的触发栅极电压。 在其最简单的实施例中，ESD钳位电路仅包括FET元件和电阻元件。 因此，与其他ESD保护电路相比，单个FET元件ESD钳位电路可能较小。 ESD钳位电路的简单性可以使寄生电容最小化，从而在宽频率范围内最大化ESD钳位电路的线性度。

公开(公告)号：US07952150B1

公开(公告)日：2011-05-31

申请号：US12479290

申请日：2009-06-05

申请人： Walter A. Wohlmuth

发明人： Walter A. Wohlmuth

IPC分类号： H01L27/88

CPC分类号： H01L29/7785 ,  H01L21/28264 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/7784 ,  H01L29/78 ,  H01L29/8128

摘要： The present invention relates to providing an enhancement-mode (e-mode) Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) with a complementary depletion-mode (d-mode) FET on a common group III-V substrate. The depletion mode FET may be another MOSFET, a MEtal-Semiconductor FET (MESFET), a High Electron Mobility Transistor (HEMT), or like FET structure. In particular, the e-mode MOSFET includes a gate structure that resides between source and drain structures on a transistor body. The gate structure includes a gate contact that is separated from the transistor body by a gate oxide. The gate oxide is an oxidized material that includes Indium and Phosphorus. The gate oxide is formed beneath the gate contact.

摘要翻译： 本发明涉及在公共III-V族基板上提供具有互补耗尽型（d模式）FET的增强型（e-mode）金属氧化物半导体场效应晶体管（MOSFET）。 耗尽型FET可以是另一种MOSFET，MEtal-Semiconductor FET（MESFET），高电子迁移率晶体管（HEMT）或类似的FET结构。 特别地，e模式MOSFET包括位于晶体管本体上的源极和漏极结构之间的栅极结构。 栅极结构包括通过栅极氧化物与晶体管本体分离的栅极接触。 栅极氧化物是包括铟和磷的氧化材料。 栅极氧化物形成在栅极接触之下。

公开(公告)号：US07881029B1

公开(公告)日：2011-02-01

申请号：US12168178

申请日：2008-07-07

申请人： Jason Yuxin Li ,  Walter A. Wohlmuth ,  Swaminathan Muthukrishnan ,  Christian Rye Iversen ,  Nathaniel Peachey

发明人： Jason Yuxin Li ,  Walter A. Wohlmuth ,  Swaminathan Muthukrishnan ,  Christian Rye Iversen ,  Nathaniel Peachey

IPC分类号： H02H3/22

CPC分类号： H03F1/52 ,  H01Q1/50 ,  H03F2200/441

摘要： The present invention relates to an electrostatic discharge (ESD) clamp circuit that is used to protect other circuitry from high voltage ESD events. The ESD clamp circuit may include a field effect transistor (FET) element as a clamping element, which is triggered by using a drain-to-gate capacitance and a drain-to-gate resistance of the FET element and a resistive element as a voltage divider to divide down an ESD voltage to provide a triggering gate voltage of the FET element. In its simplest embodiment, the ESD clamp circuit includes only an FET element, a resistive element, a source-coupled level shifting diode, and a reverse protection diode. Therefore, the ESD clamp circuit may be small compared to other ESD protection circuits. The simplicity of the ESD clamp circuit may minimize parasitic capacitances, thereby maximizing linearity of the ESD clamp circuit over a wide frequency range.

摘要翻译： 本发明涉及用于保护其它电路免受高电压ESD事件的静电放电（ESD）钳位电路。 ESD钳位电路可以包括作为钳位元件的场效应晶体管（FET）元件，其通过使用FET元件的漏极 - 栅极电容和漏极 - 栅极电阻和电阻元件作为电压来触发 以分隔ESD电压以提供FET元件的触发栅极电压。 在其最简单的实施例中，ESD钳位电路仅包括FET元件，电阻元件，源极耦合电平移位二极管和反向保护二极管。 因此，与其他ESD保护电路相比，ESD钳位电路可能较小。 ESD钳位电路的简单性可以使寄生电容最小化，从而在宽频率范围内最大化ESD钳位电路的线性度。

公开(公告)号：US07656002B1

公开(公告)日：2010-02-02

申请号：US11947840

申请日：2007-11-30

申请人： Curtis A. Barratt ,  Michael T. Fresina ,  Brian G. Moser ,  Dain C. Miller ,  Walter A. Wohlmuth

发明人： Curtis A. Barratt ,  Michael T. Fresina ,  Brian G. Moser ,  Dain C. Miller ,  Walter A. Wohlmuth

IPC分类号： H01L31/058 ,  H01L21/8238

CPC分类号： H01L27/0605 ,  H01L21/8252 ,  H01L29/7371 ,  H01L29/7785

摘要： The present invention relates to a microelectronic device having a bipolar epitaxial structure that provides at least one bipolar transistor element formed over at least one field effect transistor (FET) epitaxial structure that provides at least one FET element. The epitaxial structures are separated with at least one separation layer. Additional embodiments of the present invention may use different epitaxial layers, epitaxial sub-layers, metallization layers, isolation layers, layer materials, doping materials, isolation materials, implant materials, or any combination thereof.

摘要翻译： 本发明涉及一种具有双极外延结构的微电子器件，其提供至少一个在提供至少一个FET元件的场效应晶体管（FET）外延结构上形成的双极晶体管元件。 用至少一个分离层分离外延结构。 本发明的另外的实施例可以使用不同的外延层，外延子层，金属化层，隔离层，层材料，掺杂材料，隔离材料，植入材料或其任何组合。

公开(公告)号：US06697412B2

公开(公告)日：2004-02-24

申请号：US09834832

申请日：2001-04-13

申请人： Edward A. Beam, III ,  Gary A. Evans ,  Paul Saunier ,  Ming-Yih Kao ,  David M. Fanning ,  William H. Davenport ,  Andy Turudic ,  Walter A. Wohlmuth

发明人： Edward A. Beam, III ,  Gary A. Evans ,  Paul Saunier ,  Ming-Yih Kao ,  David M. Fanning ,  William H. Davenport ,  Andy Turudic ,  Walter A. Wohlmuth

IPC分类号： H01S5183

CPC分类号： H01L33/30 ,  B82Y20/00 ,  H01S5/0218 ,  H01S5/183 ,  H01S5/3409 ,  H01S5/3434

摘要： A light-emitting device includes a GaAs substrate, a light-emitting structure disposed above the substrate and capable of emitting light having a wavelength of about 1.3 microns to about 1.55 microns, and a buffer layer disposed between the substrate and the light-emitting structure. The composition of the buffer layer varies through the buffer layer such that a lattice constant of the buffer layer grades from a lattice constant approximately equal to a lattice constant of the substrate to a lattice constant approximately equal to a lattice constant of the light-emitting structure. The light-emitting device exhibits improved mechanical, electrical, thermal, and optical properties compared to similar light-emitting devices grown on InP substrates.

摘要翻译： 发光器件包括GaAs衬底，设置在衬底上方并能够发射波长约1.3微米至约1.55微米的光的发光结构，以及设置在衬底和发光结构之间的缓冲层 。 缓冲层的组成通过缓冲层变化，使得缓冲层的晶格常数从基本等于晶格常数的晶格常数等于晶体常数近似等于发光结构的晶格常数 。 与在InP衬底上生长的类似发光器件相比，发光器件具有改进的机械，电学，热学和光学性能。