公开(公告)号：US11488873B2

公开(公告)日：2022-11-01

申请号：US17018084

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/285

Abstract: A method includes depositing a first conductive layer over a gate dielectric layer; depositing a first work function tuning layer over the first conductive layer; selectively removing the first work function tuning layer from over a first region of the first conductive layer; doping the first work function tuning layer with a dopant; and after doping the first work function tuning layer performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function tuning layer. The first treatment process etches the first conductive layer at a greater rate than the first work function tuning layer.

公开(公告)号：US20220328319A1

公开(公告)日：2022-10-13

申请号：US17854175

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/285 ,  H01L29/786 ,  H01L29/06 ,  H01L27/092 ,  H01L29/40 ,  H01L21/8238 ,  H01L29/423

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nano structure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.

公开(公告)号：US11443979B2

公开(公告)日：2022-09-13

申请号：US16836930

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Da-Yuan Lee

IPC: H01L21/768 ,  H01L21/027 ,  H01L29/66

Abstract: A semiconductor device may include a substrate, a first transistor disposed on the substrate, and a second transistor disposed on the substrate. The first transistor includes a first gate structure. The first gate structure of the first transistor may include a first high-k layer, a first work function layer, an overlying work function layer, and a first capping layer sequentially disposed on the substrate. The second transistor includes a second gate structure. The second gate structure comprises a second gate structure, the second gate structure comprising a second high-k layer, a second work function layer, and a second capping layer sequentially disposed on the substrate. The first capping layer and the second capping layer comprise a material having higher resistant to oxygen or fluorine than materials of the second work function layer and the overlying work function layer.

公开(公告)号：US20220285159A1

公开(公告)日：2022-09-08

申请号：US17325736

申请日：2021-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/3115

Abstract: In some embodiments, a method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form first recesses; forming source/drain regions in the first recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; performing an aluminum treatment on the gate dielectric; depositing a first conductive material over and around the gate dielectric; performing a fluorine treatment on the first conductive material; and depositing a second conductive material over and around the first conductive material.

公开(公告)号：US11437240B2

公开(公告)日：2022-09-06

申请号：US17078911

申请日：2020-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/285 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L21/8238 ,  H01L27/092

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nanostructure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.

公开(公告)号：US11411079B1

公开(公告)日：2022-08-09

申请号：US17198650

申请日：2021-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02

Abstract: A method of forming semiconductor devices having improved work function layers and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes depositing a gate dielectric layer on a channel region over a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and after performing the oxygen treatment, depositing a second p-type work function metal on the first p-type work function metal.

公开(公告)号：US20220238648A1

公开(公告)日：2022-07-28

申请号：US17220335

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Jia-Ming Lin ,  Chi On Chui

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/265

Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.

公开(公告)号：US11362002B2

公开(公告)日：2022-06-14

申请号：US16870485

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  C23C16/455 ,  H01L21/285 ,  H01L21/28 ,  H01L21/764 ,  H01L27/088 ,  H01L29/08 ,  H01L29/06 ,  H01L29/49 ,  H01L29/45 ,  C23C16/34

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. After the recessing, a portion of a semiconductor material between the isolation region protrudes higher than top surfaces of the isolation regions to form a semiconductor fin. The method further includes forming a gate stack, which includes forming a gate dielectric on sidewalls and a top surface of the semiconductor fin, and depositing a titanium nitride layer over the gate dielectric as a work-function layer. The titanium nitride layer is deposited at a temperature in a range between about 300° C. and about 400° C. A source region and a drain region are formed on opposing sides of the gate stack.

公开(公告)号：US20220173222A1

公开(公告)日：2022-06-02

申请号：US17676380

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Hsin-Yi Lee ,  Hsuan-Yu Tung ,  Chin-You Hsu ,  Cheng-Lung Hung

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.

公开(公告)号：US20210398861A1

公开(公告)日：2021-12-23

申请号：US17018084

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/092

Abstract: A method includes depositing a first conductive layer over a gate dielectric layer; depositing a first work function tuning layer over the first conductive layer; selectively removing the first work function tuning layer from over a first region of the first conductive layer; doping the first work function tuning layer with a dopant; and after doping the first work function tuning layer performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function tuning layer. The first treatment process etches the first conductive layer at a greater rate than the first work function tuning layer.