公开(公告)号：US10522114B2

公开(公告)日：2019-12-31

申请号：US15992642

申请日：2018-05-30

Applicant: Intel Corporation

Inventor： Jeffery S. Boles ,  Hema C. Nalluri ,  Balaji Vembu ,  Michael Apodaca ,  Altug Koker ,  Lalit K. Saptarshi

IPC: G06F12/0846 ,  G06F3/06 ,  G06T1/60 ,  G09G5/36 ,  G06T1/20 ,  G06F12/0895 ,  G06F12/0875

Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.

公开(公告)号：US10521876B2

公开(公告)日：2019-12-31

申请号：US15489040

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Louis Feng ,  Altug Koker ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M. Cimini

IPC: G06T1/20 ,  G06T11/40 ,  G06T1/60 ,  G06F9/50

Abstract: Systems, methods and apparatuses may provide for deferred geometry rasterization technology that includes a decision controller to determine, based on available resources in a graphics processor and a view frustum, a first portion of graphics information to be output to the graphics processor and a storage device communicatively coupled to the decision controller to store a second portion of the graphics information for future use. Additionally, an output handler may output the first portion of the graphics information to the graphics processor and swap out the second portion for unused graphics information on the graphics processor.

公开(公告)号：US20190391871A1

公开(公告)日：2019-12-26

申请号：US16284912

申请日：2019-02-25

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray

IPC: G06F11/10 ,  G06T1/60 ,  G06T15/00 ,  G11C29/52

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive metadata from an application, wherein the meta data indicates one or more processing operations which can accommodate a predetermined level of bit errors in read operations from memory, determine, from the metadata, pixel data for which error correction code bypass is acceptable, and generate one or more error correction code bypass hints for subsequent cache access to the pixel data for which error correction code bypass is acceptable, and transmit the one or more error correction code bypass hints to a graphics processing pipeline. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190362772A1

公开(公告)日：2019-11-28

申请号：US16435878

申请日：2019-06-10

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Iqbal R. Rajwani ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Altug Koker ,  Abhisek R. Appu

IPC: G11C11/4094 ,  G06F9/38 ,  G11C11/4074 ,  G06F12/08 ,  G06F12/109 ,  G06F12/1027 ,  G06F12/0897 ,  G06F12/0868 ,  G06F13/40 ,  G06F3/06 ,  G06F9/30 ,  G11C11/4093

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

公开(公告)号：US10482028B2

公开(公告)日：2019-11-19

申请号：US15493757

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06F12/0895 ,  G06F12/126 ,  G06F12/02 ,  G06T1/60

Abstract: A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.

公开(公告)号：US10453427B2

公开(公告)日：2019-10-22

申请号：US15477030

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  James A. Valerio ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Vasanth Ranganathan ,  Kalyan Bhairavabhatla ,  Arthur D. Hunter, Jr. ,  Wei-Yu Chen ,  Subramaniam M. Maiyuran

IPC: G09G5/36 ,  G06F9/46 ,  G06F12/0875 ,  G09G5/00 ,  G06F12/084 ,  G06F12/0811

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

公开(公告)号：US10452586B2

公开(公告)日：2019-10-22

申请号：US15488929

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kiran C Veernapu ,  Balaji Vembu ,  Vasanth Ranganathan ,  Prasoonkumar Surti

IPC: G06F13/40 ,  G06F12/0846 ,  G06F9/54 ,  G06F13/42 ,  G06T1/60 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0831

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to monitor a thread switching overhead parameter for an application executing in a processing system and in response to a determination that the thread switching overhead parameter exceeds a threshold, to activate a thread management algorithm to reduce thread switching in the processing system. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190317771A1

公开(公告)日：2019-10-17

申请号：US16388444

申请日：2019-04-18

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G06F9/38 ,  G06F9/48 ,  G06F9/54 ,  G06F12/0866 ,  G06F9/50 ,  G06T1/20 ,  G06F15/16 ,  G06F15/76 ,  G06F9/52 ,  G06F9/46 ,  G06T1/60 ,  G06F12/0897

Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.

公开(公告)号：US10444817B2

公开(公告)日：2019-10-15

申请号：US15488662

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Bhushan M. Borole ,  Wenyin Fu ,  Kamal Sinha ,  Joydeep Ray

IPC: G09G5/36 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3296

Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

公开(公告)号：US20190287290A1

公开(公告)日：2019-09-19

申请号：US16271368

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Michael Apodaca ,  Kai Xiao ,  Altug Koker ,  Jeffery S. Boles ,  Adam T. Lake ,  Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  James M. Holland ,  Prasoonkumar Surti ,  Jonathan Kennedy ,  Louis Feng ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: G06T15/06 ,  G06F3/01 ,  H04S7/00 ,  G06T19/00 ,  G06T15/00

Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.