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公开(公告)号：US11145115B2
公开(公告)日：2021-10-12
申请号：US16233610
申请日：2018-12-27
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Balaji Vembu , Hema C. Nalluri , Michael Apodaca , Jeffery S. Boles
Abstract: By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments.
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公开(公告)号：US10885880B2
公开(公告)日：2021-01-05
申请号：US16710491
申请日：2019-12-11
Applicant: Intel Corporation
Inventor： Jeffery S. Boles , Hema C. Nalluri , Balaji Vembu , Michael Apodaca , Altug Koker , Lalit K. Saptarshi
IPC: G06F3/06 , G09G5/36 , G06T1/60 , G06F12/0846 , G06T1/20 , G06F12/0895 , G06F12/0875
Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.
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公开(公告)号：US10192281B2
公开(公告)日：2019-01-29
申请号：US15204402
申请日：2016-07-07
Applicant: Intel Corporation
Inventor： Jeffery S. Boles , Hema C. Nalluri , Balaji Vembu , Pritav H. Shah , Michael Apodaca , Murali Ramadoss , Lalit K. Saptarshi
Abstract: A mechanism for command stream processing is described. A method of embodiments, as described herein, includes fetching cache lines from a memory to fill command first in first out buffer (FIFO), wherein the fetched cachelines an overfetching of data necessary to process a command, a first parser to fetch and execute batch commands stored in the command FIFO and a second parser to fetch commands and execute the batch commands and non-batch commands stored in the command FIFO.
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公开(公告)号：US10672176B2
公开(公告)日：2020-06-02
申请号：US15692951
申请日：2017-08-31
Applicant: Intel Corporation
Inventor： Hema C. Nalluri , Balaji Vembu , Peter L. Doyle , Michael Apodaca , Jeffery S. Boles
Abstract: An apparatus and method are described for culling commands in a tile-based renderer. For example, one embodiment of an apparatus comprises: a command buffer to store a plurality of commands to be executed by a render pipeline to render a plurality of tiles; visibility analysis circuitry to determine per-tile visibility information for each of the plurality of tiles and to store the visibility information for a first tile in a first storage, the visibility information specifying either that all of the commands associated with rendering the first tile can be skipped or identifying individual commands associated with rendering the first tile that can be skipped; and a render pipeline to read the visibility information from the first storage to determine whether to execute or skip one or more of the commands from the command buffer to render the first tile.
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公开(公告)号：US10210655B2
公开(公告)日：2019-02-19
申请号：US14865933
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Balaji Vembu , Hema C. Nalluri , Michael Apodaca , Jeffery S. Boles
Abstract: By scheduling/managing workload submission to a position only shading pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments. An interface submits workloads to a slave engine running in one parallel pipe to assist a main engine running in another parallel pipe. Command sequences for each parallel pipe are separated to enable the slave engine to run ahead of the main engine. The slave engine is a position only shader and the main engine is a render engine.
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Patent Agency Ranking
公开(公告)号：US20170010894A1
公开(公告)日：2017-01-12
申请号：US14794521
申请日：2015-07-08
Applicant: Intel Corporation
Inventor： Hema C. Nalluri , Supratim Pal , Subramaniam Maiyuran , Joy Chandra
IPC: G06F9/30
Abstract: Systems, apparatuses and methods may provide for associating a first instruction pointer with an IF block of a primary IF-ELSE conditional construct associated with a thread and activating a second instruction pointer in response to a dependency associated with the IF block. Additionally, the second instruction pointer may be associated with an ELSE block of the primary IF-ELSE conditional construct. In one example, the IF block and the ELSE block are executed, via the first instruction pointer and the second instruction pointer, one or more of independently from or parallel to one another.
Abstract translation: 系统，装置和方法可以提供将第一指令指针与与线程相关联的主IF-ELSE条件结构的IF块相关联，并且响应于与IF块相关联的依赖关系来激活第二指令指针。 另外，第二指令指针可以与主IF-ELSE条件构造的ELSE块相关联。 在一个示例中，IF块和ELSE块经由第一指令指针和第二指令指针执行独立于或彼此平行的一个或多个。
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7.发明申请公开(公告)号：US20140300614A1
公开(公告)日：2014-10-09
申请号：US14128536
申请日：2012-12-18
Applicant: INTEL CORPORATION
Inventor： Hema C. Nalluri , Peter L. Doyle , Jeffrey S. Boles , Joy Chandra
IPC: G06T1/20
CPC classification number: G06T1/20 , G06F9/30072 , G06F9/30076 , G06F9/3879
Abstract: Programmable predication logic in command streamer instruction execution is described. In one example, the invention includes a method that includes receiving batch buffer execution start command at a command streamer, the batch buffer containing executable instructions, determining whether predication has been enabled for the instructions using the start command, if predication has been enabled, then comparing a predication condition to values stored in a predication register, and if the condition is satisfied by the predication register values, then executing the batch buffer.
Abstract translation: 描述了命令流指令执行中的可编程预测逻辑。 在一个示例中，本发明包括一种方法，其包括在命令流分发器处接收批处理缓冲器执行开始命令，批量缓冲器包含可执行指令，如果已经启用了预测，则确定是否已经启用了使用开始命令的指令的指令， 将预测条件与存储在预测寄存器中的值进行比较，并且如果条件由预测寄存器值满足，则执行批量缓冲器。
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公开(公告)号：US10789071B2
公开(公告)日：2020-09-29
申请号：US14794521
申请日：2015-07-08
Applicant: Intel Corporation
Inventor： Hema C. Nalluri , Supratim Pal , Subramaniam Maiyuran , Joy Chandra
Abstract: Systems, apparatuses and methods may provide for associating a first instruction pointer with an IF block of a primary IF-ELSE conditional construct associated with a thread and activating a second instruction pointer in response to a dependency associated with the IF block. Additionally, the second instruction pointer may be associated with an ELSE block of the primary IF-ELSE conditional construct. In one example, the IF block and the ELSE block are executed, via the first instruction pointer and the second instruction pointer, one or more of independently from or parallel to one another.
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公开(公告)号：US10303902B2
公开(公告)日：2019-05-28
申请号：US15495644
申请日：2017-04-24
Applicant: INTEL CORPORATION
Inventor： Hema C. Nalluri , Aditya Navale , Murali Ramadoss
Abstract: Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged. A graphics processing unit (GPU) can receive the privilege-designated batch buffers from the KMD, and is configured to disallow execution of any privileged command from a non-privileged batch buffer, while any privileged commands from privileged batch buffers are unrestricted by the GPU
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公开(公告)号：US20190130635A1
公开(公告)日：2019-05-02
申请号：US16233610
申请日：2018-12-27
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Balaji Vembu , Hema C. Nalluri , Michael Apodaca , Jeffery S. Boles
Abstract: By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments.
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