Invention Grant
- Patent Title: Hardware assist for privilege access violation checks
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Application No.: US15495644Application Date: 2017-04-24
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Publication No.: US10303902B2Publication Date: 2019-05-28
- Inventor: Hema C. Nalluri , Aditya Navale , Murali Ramadoss
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- Main IPC: G06F21/74
- IPC: G06F21/74 ; G06F21/84 ; G06T15/00

Abstract:
Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged. A graphics processing unit (GPU) can receive the privilege-designated batch buffers from the KMD, and is configured to disallow execution of any privileged command from a non-privileged batch buffer, while any privileged commands from privileged batch buffers are unrestricted by the GPU
Public/Granted literature
- US20170357831A1 HARDWARE ASSIST FOR PRIVILEGE ACCESS VIOLATION CHECKS Public/Granted day:2017-12-14
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