公开(公告)号：US20070040226A1

公开(公告)日：2007-02-22

申请号：US11446201

申请日：2006-06-05

Applicant: Hirotaka Amasuga ,  Takayuki Matsuzuka ,  Akira Inoue

Inventor： Hirotaka Amasuga ,  Takayuki Matsuzuka ,  Akira Inoue

IPC: H01L29/76

CPC classification number: H03F1/223 ,  H01L27/0222 ,  H01L27/0629 ,  H03F3/195 ,  H03F2200/451 ,  H03F2200/75

Abstract: A cascode circuit in which two field effect transistors “FET”) are connected in cascode has a first FET having its source grounded, a second FET having its source connected to the drain of the first FET, and a Schottky barrier diode having an anode connected to the source of the first FET and a cathode connected to the gate of the second FET.

Abstract translation: 其中两个场效应晶体管“FET”）串联连接的共源共栅电路具有其源极接地的第一FET，其源极连接到第一FET的漏极的第二FET和具有阳极连接的肖特基势垒二极管 到第一FET的源极和连接到第二FET的栅极的阴极。

公开(公告)号：US20060249761A1

公开(公告)日：2006-11-09

申请号：US10539008

申请日：2003-12-16

Applicant: Akira Inoue ,  Masahiko Hata

Inventor： Akira Inoue ,  Masahiko Hata

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/7371 ,  H01L29/1004

Abstract: In an epitaxial substrate comprising a bipolar transistor structure having a collector layer (3), base layer (4) and emitter layer (5) on a GaAs substrate (2), the base layer (4) is configured a lower base layer (41) having a required carrier concentration, an upper base layer (42), and a low carrier concentration layer (43) provided between the lower base layer (41) and the upper base layer (42) that has a ballast effect. The lower base layer (41) or the upper base layer (42) may be omitted. The higher the temperature of the low carrier concentration layer (43) portion is, the easier it is for electrons to pass therethrough, which has the effect of raising the amplification factor, thereby helping the transistor heat stability characteristics.

Abstract translation: 在包括在GaAs衬底（2）上具有集电极层（3），基底层（4）和发射极层（5））的双极晶体管结构的外延衬底中，基底层（4）被构造为下部基底层 ）具有设置在具有镇流效应的下基底层（41）和上基底层（42）之间的上基底层（42）和低载流子浓度层（43）。 可以省略下基层（41）或上基层（42）。 低载流子浓度层（43）部分的温度越高，电子越容易通过，这具有提高放大系数的作用，从而有助于晶体管的热稳定性。

公开(公告)号：US07084026B2

公开(公告)日：2006-08-01

申请号：US10913383

申请日：2004-08-09

Applicant: Takeshi Takagi ,  Akira Inoue

Inventor： Takeshi Takagi ,  Akira Inoue

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L29/802 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/78687

Abstract: A region of an Si layer 15 located between source and drain regions 19 and 20 is an Si body region 21 which contains an n-type impurity of high concentration. An Si layer 16 and an SiGe layer 17 are, in an as grown state, undoped layers into which no n-type impurity is doped. Regions of the Si layer 16 and the SiGe layer 17 located between the source and drain regions 19 and 20 are an Si buffer region 22 and an SiGe channel region 23, respectively, which contain the n-type impurity of low concentration. A region of an Si film 18 located directly under a gate insulating film 12 is an Si cap region 24 into which a p-type impurity (5×1017 atoms·cm−3) is doped. Accordingly, a semiconductor device in which an increase in threshold voltage is suppressed can be achieved.

Abstract translation: 位于源区和漏区19和20之间的Si层15的区域是含有高浓度的n型杂质的Si体区21。 处于生长状态的Si层16和SiGe层17未掺杂n型杂质的未掺杂层。 位于源区和漏区19和20之间的Si层16和SiGe层17的区域分别是含有低浓度的n型杂质的Si缓冲区22和SiGe沟道区23。 位于栅极绝缘膜12正下方的Si膜18的区域是Si帽区域24，其中p型杂质（5×10 17原子％-3重量％ ）掺杂。 因此，可以实现抑制阈值电压增加的半导体装置。

公开(公告)号：US20060054944A1

公开(公告)日：2006-03-16

申请号：US11260197

申请日：2005-10-28

Applicant: Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

Inventor： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/78696 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78687 ,  Y10S438/933 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.

Abstract translation: 本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。 其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。 根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

公开(公告)号：US20050251709A1

公开(公告)日：2005-11-10

申请号：US10516819

申请日：2003-06-27

Applicant: Chisato Kemmochi ,  Akira Inoue ,  Masayuki Nishiguchi

Inventor： Chisato Kemmochi ,  Akira Inoue ,  Masayuki Nishiguchi

IPC: G10H7/10 ,  G10H7/12 ,  H03B28/00 ,  G06K5/04

CPC classification number: G10H7/12 ,  G10H7/10 ,  G10H2250/121 ,  G10H2250/225 ,  H03B28/00

Abstract: Amplitude, phase and frequency of a sine wave to be generated are calculated on the basis of feature quantity s1 delivered to feature quantity detecting means (2), and are sent to initialization means (3). The initialization means (3) calculates first two points of the sine wave to send the points thus calculated to oscillator (sine wave generating means) (4) as initial value s4. The oscillator (4) sequentially calculates values of respective sample points of waveform by using recurrence formula in accordance with initial value or values instructed from the initialization means (3) to thereby generate a sine wave signal. Thus, sine wave generation is performed without performing modulo-addressing.

Abstract translation: 基于递送到特征量检测装置（2）的特征量s 1计算要产生的正弦波的幅度，相位和频率，并将其发送到初始化装置（3）。 初始化装置（3）计算正弦波的前两点，将由此计算的点发送到振荡器（正弦波产生装置）（4）作为初始值s 4。 振荡器（4）通过使用根据从初始化装置（3）指示的初始值或值产生正弦波信号的递归公式，顺序地计算各波形采样点的值。 因此，在不执行模寻址的情况下执行正弦波生成。

公开(公告)号：US20050231673A1

公开(公告)日：2005-10-20

申请号：US10928447

申请日：2004-08-30

Applicant: Katsunori Yamazaki ,  Eiji Okamoto ,  Tsuyoshi Maeda ,  Kimitaka Kamijo ,  Daisuke Nagano ,  Takumi Seki ,  Akira Inoue

Inventor： Katsunori Yamazaki ,  Eiji Okamoto ,  Tsuyoshi Maeda ,  Kimitaka Kamijo ,  Daisuke Nagano ,  Takumi Seki ,  Akira Inoue

IPC: G02F1/1365 ,  G02F1/133 ,  G02F1/1343 ,  G02F1/136 ,  G09F9/30 ,  H01L49/02

CPC classification number: G02F1/134363 ,  G02F1/1365

Abstract: To simplify a manufacturing process of a transverse electric field mode liquid crystal display device by using a non-linear resistance element such as a TFD (Thin Film Diode) as a switching element. In a liquid crystal display device having a pair of substrates with liquid crystal interposed therebetween, one of the substrates consists of an electrode substrate. On the electrode substrate, there are provided a first group of electrodes, a second group of electrodes crossing the first group of electrodes with an insulating layer interposed therebetween, non-linear resistance elements, one end of each of the non-linear resistance elements being connected to the respective one of the second group of electrodes, and pixel electrodes opposing the first group of electrodes, each pixel electrode being connected to the other end of each of the non-linear resistance elements. Since the non-linear resistance elements have a so-called TFD (MIM) structure made of metal-insulating layer-metal, the manufacturing process is simple. Therefore, it is possible to manufacture the transverse electric field mode display device at low cost.

Abstract translation: 为了简化通过使用诸如TFD（薄膜二极管）之类的非线性电阻元件作为开关元件的横向电场模式液晶显示装置的制造过程。 在具有插入液晶的一对基板的液晶显示装置中，一个基板由电极基板构成。 在电极基板上设置有第一组电极，与第一组电极交叉的第二组电极，绝缘层插入其间，非线性电阻元件，每个非线性电阻元件的一端为 连接到第二组电极中的相应一个，以及与第一组电极相对的像素电极，每个像素电极连接到每个非线性电阻元件的另一端。 由于非线性电阻元件具有由金属绝缘层金属制成的所谓的TFD（MIM）结构，所以制造工艺简单。 因此，可以以低成本制造横电场模式显示装置。

公开(公告)号：US20050231286A1

公开(公告)日：2005-10-20

申请号：US11066765

申请日：2005-02-28

Applicant: Seiki Gotou ,  Akira Inoue

Inventor： Seiki Gotou ,  Akira Inoue

IPC: H03F1/02 ,  H03F1/07 ,  H03F3/193 ,  H03F3/60 ,  H03F3/68 ,  H05K1/05 ,  H05K1/14

CPC classification number: H03F3/60 ,  H03F1/0288 ,  H03F3/604 ,  H05K1/05 ,  H05K1/141

Abstract: In a power amplifier a Doherty amplifier is provided with an output higher harmonic reflection circuit that is connected to the output terminal of a first FET chip and sets an even-numbered higher harmonic load of an output signal at the output terminal to be a short-circuit, or at a low impedance approximating a short-circuit, and sets an odd-numbered higher harmonic load of an output signal at the output terminal to be an open-circuit, or a high impedance approximating an open-circuit.

Abstract translation: 在功率放大器中，Doherty放大器设置有输出高次谐波反射电路，其连接到第一FET芯片的输出端，并将输出端的输出信号的偶数高次谐波负载设置为短路， 或接近短路的低阻抗，并且将输出端子处的输出信号的奇数高次谐波负载设置为开路或接近开路的高阻抗。

公开(公告)号：US06917091B2

公开(公告)日：2005-07-12

申请号：US10770414

申请日：2004-02-04

Applicant: Akira Inoue ,  Seiki Gotou

Inventor： Akira Inoue ,  Seiki Gotou

IPC: H01L21/338 ,  H01L23/482 ,  H01L29/812 ,  H01L29/00

CPC classification number: H01L23/4824 ,  H01L23/4821 ,  H01L24/06 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2924/1306 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A high power semiconductor device including gate electrodes also includes an active region of an approximately rectangular shape, located on a semiconductor substrate; a drain electrode located on the active region; and first and second source electrodes which are disposed on opposite sides to the drain electrode so that the first and second source electrodes face each other across at least some of the gate electrodes. The directions of currents carried by the first and second source electrodes are opposite to each other.

Abstract translation: 包括栅电极的高功率半导体器件还包括位于半导体衬底上的大致矩形形状的有源区; 位于有源区上的漏电极; 以及第一和第二源电极，其设置在与漏电极相对的两侧，使得第一和第二源电极在至少一些栅电极之间彼此面对。 由第一和第二源电极承载的电流的方向彼此相反。

公开(公告)号：US06915045B2

公开(公告)日：2005-07-05

申请号：US10651287

申请日：2003-08-29

Applicant: Ken Hashimoto ,  Manabu Shiozaki ,  Toshikazu Shibata ,  Akira Inoue

Inventor： Ken Hashimoto ,  Manabu Shiozaki ,  Toshikazu Shibata ,  Akira Inoue

IPC: G02B5/18 ,  G02B6/02 ,  G02B6/293 ,  G02B6/34 ,  H04J14/02

CPC classification number: G02B6/2938 ,  G02B6/02085 ,  G02B6/02138 ,  G02B6/02152 ,  G02B6/2932

Abstract: The present invention relates to an optical waveguide type grating element and others in structure for decreasing absolute values of chromatic dispersion occurring in selective reflection of each of signal channels in a reflection band. The optical waveguide type grating element is provided with an optical waveguide in which signal light containing a plurality of signal channels spaced at a channel spacing λi propagates, and a grating which is an index modulation formed over a predetermined range of the optical waveguide. Particularly, the optical waveguide type grating element has a transmittance of −20 dB or less for each of the signal channels in the reflection band, and has a reflectance of −20 dB or less for each of signal channels outside the reflection band. Furthermore, a deviation of a group delay time of each of the signal channels in the reflection band, which is caused by reflection in the grating, is 10 ps or less in a wavelength range of (λCH−λi×0.375/2) or more but (λCH+λi×0.375/2) or less, where λCH is a center wavelength of each signal channel.

Abstract translation: 本发明涉及光波导型光栅元件等结构，用于降低在反射带中每个信号通道的选择反射中出现的色散绝对值。 光波导型光栅元件设置有光波导，其中包含以信道间隔λ1隔开的多个信号通道的信号光传播，并且是在预定的波长上形成的索引调制的光栅 光波导的范围。 特别地，光波导型光栅元件对于反射带中的每个信号通道具有-20dB或更小的透射率，并且对于反射带外的每个信号通道具有-20dB或更小的反射率。 此外，由于光栅中的反射引起的反射带中的每个信号通道的群组延迟时间的偏差在（λ-CH-）的波长范围内为10ps以下， λλx x 0.375 / 2）或更小，但是（λ/ CH 2 +λ1 x 0.375 / 2）或更小，其中λ< SUB> CH 是每个信号通道的中心波长。

公开(公告)号：US20050134899A1

公开(公告)日：2005-06-23

申请号：US10925584

申请日：2004-08-25

Applicant: Akira Inoue

Inventor： Akira Inoue

IPC: G06F3/12 ,  G06F15/00 ,  G06K15/02

CPC classification number: G06K15/1817 ,  G06F3/1213 ,  G06F3/122 ,  G06F3/124 ,  G06F3/126 ,  G06F3/1267 ,  G06F3/1275 ,  G06F3/1285 ,  G06K15/02

Abstract: The purpose of this invention is to provide a printer apparatus capable of receiving concurrent input print data from plural input ports without increasing receiving buffer memory and image creator. A controller determines whether an image creator is used by other jobs when starting receiving print data through any one of the plural input ports. When not used, print data related to the current job is stored in a receiving buffer memory and at the same time create print data stored in the buffer memory via the image creator. On the other hand, when other jobs use the image creator, the print data related to the current job is stored in a hard disk unit and then is created the print data stored in the hard disk unit when the image creating device becomes available.

Abstract translation: 本发明的目的是提供一种能够在不增加接收缓冲存储器和图像创建者的情况下从多个输入端口接收并发输入打印数据的打印机装置。 当通过多个输入端口中的任何一个开始接收打印数据时，控制器确定其他作业是否使用图像创建器。 当不使用时，与当前作业相关的打印数据存储在接收缓冲存储器中，同时通过图像创建者创建存储在缓冲存储器中的打印数据。 另一方面，当其他作业使用图像创建者时，与当前作业相关的打印数据被存储在硬盘单元中，然后当图像创建设备变得可用时，创建存储在硬盘单元中的打印数据。