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    Digital mark-up in a three dimensional environment
    92.
    发明授权
    Digital mark-up in a three dimensional environment 有权

    公开(公告)号：US11880540B2

    公开(公告)日：2024-01-23

    申请号：US16966070

    申请日：2018-03-22

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Ian N. Robinson

    IPC: G06F3/00 ,  G06F9/00 ,  G06F17/00 ,  G06F3/04815 ,  G06F3/01 ,  G06F3/0482 ,  G06F3/04842 ,  G06F3/04845

    CPC classification number: G06F3/04815 ,  G06F3/011 ,  G06F3/0482 ,  G06F3/04842 ,  G06F3/04845

    Abstract: Examples disclosed herein relate to digital mark-up in a three dimensional (3D) environment. An example device for digital mark-up in a 3D environment includes a processor, a display for showing a view of the 3D environment, and a memory including instructions on the processor. When the memory stored instructions are executed on the processor, they cause the processor to generate an anchor point in response to an author input, wherein the anchor point includes a virtual location. When the memory stored instructions are executed on the processor, they cause the processor to generate a mark-up object associated with the anchor point, wherein the mark-up object includes mark-up dimensions, a virtual authoring location, and a selectable association that, in response to being selected, instructs the processor to adjust the view shown in the display to be a view from the virtual authoring location at the time the mark-up object was authored.

    Read level tracking by random threshold movement with short feedback loop
    93.
    发明授权
    Read level tracking by random threshold movement with short feedback loop 有权

    公开(公告)号：US11868646B2

    公开(公告)日：2024-01-09

    申请号：US17453047

    申请日：2021-11-01

    Applicant: Western Digital Technologies, Inc.

    Inventor： Tomer Eliash ,  Alexander Bazarsky ,  Eran Sharon

    IPC: G06F3/00 ,  G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a read threshold on a wordline, adjust a read threshold voltage level associated with the read threshold, determine an adjusted read threshold at the adjusted read threshold voltage level, where the adjusted read threshold is different from the read threshold, compare the adjusted read threshold to the read threshold, and calibrate the read threshold based on the comparing. The controller is further configured to analyze a bit error rate (BER) difference based on the calibrating and/or a previous read threshold voltage level movement, choose a next target read threshold for next calibration, and read a second page at the next target read threshold.

    Systems, devices, and methods for data migration
    97.
    发明授权
    Systems, devices, and methods for data migration 有权

    公开(公告)号：US11853578B2

    公开(公告)日：2023-12-26

    申请号：US17512588

    申请日：2021-10-27

    Applicant: Micron Technology, Inc.

    Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

    IPC: G06F3/00 ,  G06F3/06 ,  G06F12/0895 ,  G06F12/0866

    CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0679 ,  G06F3/068 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/0673 ,  G06F12/0866 ,  G06F12/0895

    Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a component, such as a controller, for facilitating a transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may receive an indication of the data migration operation from a host device and may initiate a transfer of data between the first and second memory devices. The controller may include one or more buffers to store data being transferred between the first and second memory devices. In some cases, the transfer of data between the first and second memory devices may occur within the memory system and without being transferred through the host device.

    Method and system for memory pool management
    100.
    发明授权
    Method and system for memory pool management 有权

    公开(公告)号：US11847328B1

    公开(公告)日：2023-12-19

    申请号：US17877801

    申请日：2022-07-29

    Applicant: Arista Networks, Inc.

    Inventor： Chen Jia Jang ,  Suhas Raghunath Joshi ,  Ganesan Venkataraman

    IPC: G06F3/00 ,  G06F3/06

    CPC classification number: G06F3/0629 ,  G06F3/065 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A logical table is configured with a first set of memory banks, where each logical row in the logical table comprises a corresponding memory row from each of the memory banks. Lookup instructions to access a logical row includes a bank set that lists the memory banks associated with that logical row. In response to a range of memory rows of one of the memory banks being reallocated to another logical table, a new memory bank is identified to store the data in the reallocated memory rows. Logical rows associated with the reallocated memory rows are mapped to the new memory bank. Bank sets in the lookup instructions that refer to the remapped logical rows are updated to list the new memory bank in place of the “old” memory bank.

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