公开(公告)号：US20230060826A1

公开(公告)日：2023-03-02

申请号：US17464516

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Jeffrey L. Scott ,  Laurent Isenegger ,  Robert M. Walker

IPC: G06F3/06

Abstract: A system includes a processing device that determines whether a memory bank is active and adds an activate command for a row of the memory bank accessed by an oldest command for the memory bank to a command scheduler in response to determining the memory bank is not active. The processing device determines whether the row of the memory bank has a corresponding row command in response to determining the memory bank is active. The processing device determines whether a close page mode is enabled or an open row timer has expired on the row and adds a precharge command to the command scheduler in response to determining the close page mode is enabled or the open row timer has expired. The processing device executes a command in the command scheduler based on a priority of commands included in the command scheduler.

公开(公告)号：US11586390B2

公开(公告)日：2023-02-21

申请号：US17498415

申请日：2021-10-11

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.

公开(公告)号：US20220147262A1

公开(公告)日：2022-05-12

申请号：US17580305

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.

公开(公告)号：US20220019533A1

公开(公告)日：2022-01-20

申请号：US16928999

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Cagdas Dirik, II ,  Laurent Isenegger ,  Robert M. Walker

IPC: G06F12/0806

Abstract: A method is described for managing the issuance and fulfillment of memory commands. The method includes receiving, by a cache controller of a memory subsystem, a first memory command corresponding to a set of memory devices. In response, the cache controller adds the first memory command to a cache controller command queue such that the cache controller command queue stores a first set of memory commands and sets a priority of the first memory command to either a high or low priority based on (1) whether the first memory command is of a first or second type and (2) an origin of the first memory command.

公开(公告)号：US20220019360A1

公开(公告)日：2022-01-20

申请号：US16929003

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert M. Walker

IPC: G06F3/06

Abstract: A method is described that includes receiving a plurality of streams of memory requests and each stream is associated with a source. The method further includes determining a bandwidth allocation for each stream, wherein each allocation represents a portion of a total bandwidth of a memory component managed by the subsystem and each allocation indicates a priority of a corresponding stream based on a corresponding source of each stream and assigning a set of credits to each stream based on the bandwidth allocations. The method also includes determining a memory command from a queue for issuance, wherein each memory command in the queue is associated with a stream and determining the memory command is based on the credits assigned to each stream such that commands associated with a stream with a higher number of credits is given priority for issuance over commands associated with a stream with a lower number.

公开(公告)号：US11182090B2

公开(公告)日：2021-11-23

申请号：US16195045

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/0895 ,  G06F12/0866

Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a component, such as a controller, for facilitating a transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may receive an indication of the data migration operation from a host device and may initiate a transfer of data between the first and second memory devices. The controller may include one or more buffers to store data being transferred between the first and second memory devices. In some cases, the transfer of data between the first and second memory devices may occur within the memory system and without being transferred through the host device.

公开(公告)号：US11175859B1

公开(公告)日：2021-11-16

申请号：US16929008

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Laurent Isenegger ,  Robert M. Walker

IPC: G06F3/06 ,  G06F9/48

Abstract: A method is described for managing issuance of memory commands. The method includes determining whether a number of high priority commands from a cache controller meets a first threshold. In response to meeting the first threshold, a second threshold, which indicates a maximum number of low priority commands allowed in a low latency memory command queue, is set to a first value. In response to not meeting the first threshold, the second threshold is set to a second value. The method further selects a memory command for issuance from the cache controller command queue, wherein the memory command is a high priority memory command when the number of low priority memory commands stored in the low latency memory controller command queue meets the second threshold and is a low priority memory command when the number of low priority memory commands does not meet the second threshold.

公开(公告)号：US11144240B2

公开(公告)日：2021-10-12

申请号：US16111974

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.

公开(公告)号：US20210227361A1

公开(公告)日：2021-07-22

申请号：US17204522

申请日：2021-03-17

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: H04W4/33 ,  H04L29/12 ,  H04W4/02 ,  H04B17/318 ,  H04W4/029 ,  H04B17/26 ,  H04B17/27

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US10782911B2

公开(公告)日：2020-09-22

申请号：US16195127

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.