公开(公告)号：US11809332B2

公开(公告)日：2023-11-07

申请号：US17548948

申请日：2021-12-13

Applicant: Micron Technology, Inc.

Inventor： Paul Rosenfeld ,  Robert M. Walker

IPC: G06F12/1045 ,  G06F12/02 ,  G06F12/0862 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/0238 ,  G06F12/0862 ,  G06F12/1009 ,  G06F12/1054

Abstract: An apparatus includes circuitry couplable to a host system and a memory device. The circuitry is configured to determine whether a page table maintained on the circuitry includes a physical address of the memory device corresponding to a virtual address associated with a TLB fill request from the host system. Responsive to determining that the page table includes the physical address, the circuitry provides signaling indicative of a completion to the TLB fill request to the host system, prefetch a page of data at the physical address from the memory device using the physical address from the page table, and provide signaling indicative of the page of data to the host system.

公开(公告)号：US11734071B2

公开(公告)日：2023-08-22

申请号：US17464546

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld

IPC: G06F9/50 ,  G06F12/12

CPC classification number: G06F9/5016 ,  G06F12/12 ,  G06F2212/1021

Abstract: A method includes allocating, via a tier allocation component, a first portion of data to a first tier memory component and writing the first portion of data to the first tier memory component in response to a first tier free list having an available entry. The method further includes evicting a second portion of data from the first tier memory component in response to the first tier free list being empty when the first portion of data is allocated to the first tier memory component and writing the first portion of data to the first tier memory component in response to evicting the second portion of data.

公开(公告)号：US11256437B2

公开(公告)日：2022-02-22

申请号：US16195071

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.

公开(公告)号：US11163473B2

公开(公告)日：2021-11-02

申请号：US16195018

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a data migration component, such as a driver, for facilitating the transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may indicate the data migration operation to a second component (e.g., a controller) of the memory system. The second component may initiate the transfer of data between the first memory device and the second memory device based on the receiving the indication of the data migration operation. In some cases, the transfer of data between the first memory device and the second memory device may occur within the memory system without being transferred through a host device.

公开(公告)号：US20250068361A1

公开(公告)日：2025-02-27

申请号：US18944972

申请日：2024-11-12

Applicant: Micron Technology, Inc.

Inventor： Elliott C. Cooper-Balis ,  Robert M. Walker ,  Paul Rosenfeld

IPC: G06F3/06

Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.

公开(公告)号：US12210460B2

公开(公告)日：2025-01-28

申请号：US18386911

申请日：2023-11-03

Applicant: Micron Technology, Inc.

Inventor： Paul Rosenfeld ,  Robert M. Walker

IPC: G06F12/1045 ,  G06F12/02 ,  G06F12/0862 ,  G06F12/1009

Abstract: An apparatus includes circuitry couplable to a host system and a memory device. The circuitry is configured to determine whether a page table maintained on the circuitry includes a physical address of the memory device corresponding to a virtual address associated with a TLB fill request from the host system. Responsive to determining that the page table includes the physical address, the circuitry provides signaling indicative of a completion to the TLB fill request to the host system, prefetch a page of data at the physical address from the memory device using the physical address from the page table, and provide signaling indicative of the page of data to the host system.

公开(公告)号：US20220075558A1

公开(公告)日：2022-03-10

申请号：US17017396

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Elliott C. Cooper-Balis ,  Robert M. Walker ,  Paul Rosenfeld

IPC: G06F3/06

Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.

公开(公告)号：US20200379667A1

公开(公告)日：2020-12-03

申请号：US16995122

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.

公开(公告)号：US20240061788A1

公开(公告)日：2024-02-22

申请号：US18386911

申请日：2023-11-03

Applicant: Micron Technology, Inc.

Inventor： Paul Rosenfeld ,  Robert M. Walker

IPC: G06F12/1045 ,  G06F12/02 ,  G06F12/0862 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/1054 ,  G06F12/0238 ,  G06F12/0862 ,  G06F12/1009

Abstract: An apparatus includes circuitry couplable to a host system and a memory device. The circuitry is configured to determine whether a page table maintained on the circuitry includes a physical address of the memory device corresponding to a virtual address associated with a TLB fill request from the host system. Responsive to determining that the page table includes the physical address, the circuitry provides signaling indicative of a completion to the TLB fill request to the host system, prefetch a page of data at the physical address from the memory device using the physical address from the page table, and provide signaling indicative of the page of data to the host system.

公开(公告)号：US11853605B2

公开(公告)日：2023-12-26

申请号：US17478570

申请日：2021-09-17

Applicant: Micron Technology, Inc.

Inventor： Sai Vineel Reddy Chittamuru ,  Paul Rosenfeld ,  Robert M. Walker ,  Jeffrey L. Scott

IPC: G06F3/06 ,  G06F16/215

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F16/215

Abstract: A method includes, responsive to a SET command associated with a key-value store, concurrently updating the key-value store maintained on a non-persistent memory device of a memory sub-system and a mirror of the key-value store maintained on a persistent memory device of the memory sub-system. The method further includes responsive to a GET command associated with the key-value store, retrieving a value of a key from the key-value store maintained on the non-persistent memory device.