公开(公告)号：US20230308390A1

公开(公告)日：2023-09-28

申请号：US17704103

申请日：2022-03-25

Applicant: Arista Networks, Inc.

Inventor： Maxime Daniel Lorrillere ,  Suhas Raghunath Joshi

IPC: H04L45/00 ,  H04L45/42 ,  H04L47/762 ,  H04L47/78

CPC classification number: H04L45/66 ,  H04L45/42 ,  H04L47/762 ,  H04L47/781

Abstract: A method of allocating programmable memory in a network device includes receiving a set of desired features for the network device, and determining a plurality of constraints associated with the set of desired features. The plurality of constraints are converted into a plurality of Boolean representations of the constraints, and a feasibility is evaluated for the desired features based on the plurality of constraints.

公开(公告)号：US12113708B2

公开(公告)日：2024-10-08

申请号：US17704103

申请日：2022-03-25

Applicant: Arista Networks, Inc.

Inventor： Maxime Daniel Lorrillere ,  Suhas Raghunath Joshi

IPC: H04L45/00 ,  H04L45/42 ,  H04L47/762 ,  H04L47/78

CPC classification number: H04L45/66 ,  H04L45/42 ,  H04L47/762 ,  H04L47/781

Abstract: A method of allocating programmable memory in a network device includes receiving a set of desired features for the network device, and determining a plurality of constraints associated with the set of desired features. The plurality of constraints are converted into a plurality of Boolean representations of the constraints, and a feasibility is evaluated for the desired features based on the plurality of constraints.

公开(公告)号：US11847328B1

公开(公告)日：2023-12-19

申请号：US17877801

申请日：2022-07-29

Applicant: Arista Networks, Inc.

Inventor： Chen Jia Jang ,  Suhas Raghunath Joshi ,  Ganesan Venkataraman

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/065 ,  G06F3/0604 ,  G06F3/0679

Abstract: A logical table is configured with a first set of memory banks, where each logical row in the logical table comprises a corresponding memory row from each of the memory banks. Lookup instructions to access a logical row includes a bank set that lists the memory banks associated with that logical row. In response to a range of memory rows of one of the memory banks being reallocated to another logical table, a new memory bank is identified to store the data in the reallocated memory rows. Logical rows associated with the reallocated memory rows are mapped to the new memory bank. Bank sets in the lookup instructions that refer to the remapped logical rows are updated to list the new memory bank in place of the “old” memory bank.