Apparatuses for generating an oscillation signal

    公开(公告)号:US11283456B2

    公开(公告)日:2022-03-22

    申请号:US17059480

    申请日:2019-08-05

    申请人: Intel Corporation

    摘要: An apparatus for generating an oscillation signal is provided. The apparatus includes a first oscillator configured to generate a first reference oscillation signal, and a second oscillator configured to generate a second reference oscillation signal. A frequency accuracy of the first oscillator is higher than a frequency accuracy of the second oscillator. Further, an oscillator phase noise of the second oscillator is lower than an oscillator phase noise of the first oscillator. The apparatus further includes a processing circuit configured to generate a third reference oscillation signal based on the first reference oscillation signal and the second reference oscillation signal. Additionally, the apparatus includes a phase-locked loop configured to generate the oscillation signal based on the third reference oscillation signal. A frequency of the oscillation signal is a multiple of a frequency of the third reference oscillation signal.

    DELAY ESTIMATION DEVICE AND DELAY ESTIMATION METHOD

    公开(公告)号:US20220077861A1

    公开(公告)日:2022-03-10

    申请号:US17529282

    申请日:2021-11-18

    IPC分类号: H03L7/085 H03L7/081

    摘要: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.

    SIGNALING SYSTEM WITH ADAPTIVE TIMING CALIBRATION

    公开(公告)号:US20220069975A1

    公开(公告)日:2022-03-03

    申请号:US17409594

    申请日:2021-08-23

    申请人: Rambus Inc.

    摘要: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

    CONTROL CIRCUIT OF DELAY LOCK LOOP AND CONTROL METHOD THEREOF

    公开(公告)号:US20220069827A1

    公开(公告)日:2022-03-03

    申请号:US17391035

    申请日:2021-08-02

    IPC分类号: H03L7/081

    摘要: A control circuit of delay lock loop and a control method thereof are provided. The control circuit includes a power status detector, a voltage comparator, an enable signal generator and a control signal generator. The power status detector detects a transition edge of a clock enable signal to generate a trigger signal corresponding to a variation of an operation power. The voltage comparator compares the operation power with a reference voltage to generate a comparison result. The enable signal generator sets an enable signal to an active state according to the trigger signal and sets the enable signal to a non-active state according to the comparison result. The control signal generator outputs a control clock to generate a control signal when the enable signal is in the active state.

    Variable-length clock stretcher with correction for glitches due to phase detector offset

    公开(公告)号:US11239846B1

    公开(公告)日:2022-02-01

    申请号:US17338625

    申请日:2021-06-03

    摘要: A clock stretcher includes a DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. The DLL may have a phase error that would cause a glitch in the modified clock during phase selection wraparound. The clock stretcher proactively increases the step size during wraparound by adding an offset skip parameter value to the hop code. The clock stretcher may operate from a sensed power supply without intervening voltage regulation.

    EFFICIENT ERROR REPORTING IN A LINK INTERFACE

    公开(公告)号:US20220004453A1

    公开(公告)日:2022-01-06

    申请号:US16921316

    申请日:2020-07-06

    发明人: Kelvin Wong

    摘要: A link interface is provided of a communication protocol using idle flow control digits (flits) to maintain link continuity. The link interface includes: a physical layer of the communication protocol configured to transmit and receive flits via a link, wherein the communication protocol provides for idle flits of first and second sizes for maintaining link continuity, the first size being smaller than the second size; and a data link layer configured to transmit and receive flits to/from the physical layer. The data link layer is configured to remove idle flits of the first size received from the physical layer and to report cyclic redundancy check errors of filtered first sized idle flits in a correct order in relation to other flits.

    Method and apparatus for implementing a quadrature VCO based on standard cells

    公开(公告)号:US11196428B1

    公开(公告)日:2021-12-07

    申请号:US17076200

    申请日:2020-10-21

    摘要: A Quadrature Voltage Controlled Oscillator (Quad VCO) based on standard digital cells and delay cells, is adapted to generate two high-frequency output signals that are “in quadrature”, so they both oscillate with similar frequency while exhibiting a mutual phase offset of about 90 degrees, and a) the digital cells include a mix of digital circuits used for implementing standard flip-flop circuits and standard logic gates; and b) the delay cells include circuits accepting a logic signal at their input and outputting a time-delayed version of said input signal, with a time delay that may be varied by a control voltage analog signal that determines the cell delay.

    HIGH SPEED DIGITAL PHASE INTERPOLATOR WITH DUTY CYCLE CORRECTION CIRCUITRY

    公开(公告)号:US20210367588A1

    公开(公告)日:2021-11-25

    申请号:US17395353

    申请日:2021-08-05

    申请人: Intel Corporation

    IPC分类号: H03K5/156 H03K5/14 H03L7/081

    摘要: Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-type networks in the PI mixer are decoupled, and DCC mechanism are blended in the PI mixer code decoding scheme to enable a low latency phase interpolation and duty cycle correction. The circuit comprises a first mixer circuitry controllable by a first code; a second mixer circuitry controllable by a second code; a node coupled to outputs of the first and second mixers; and a keeper circuitry coupled to the node, wherein the first and second mixers are tri-stable mixers.

    Delay estimation device and delay estimation method

    公开(公告)号:US11184009B2

    公开(公告)日:2021-11-23

    申请号:US17083304

    申请日:2020-10-29

    IPC分类号: H03L7/085 H03L7/081

    摘要: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.