- 专利标题: CONTROL CIRCUIT OF DELAY LOCK LOOP AND CONTROL METHOD THEREOF
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申请号: US17391035申请日: 2021-08-02
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公开(公告)号: US20220069827A1公开(公告)日: 2022-03-03
- 发明人: Zong-Ying Ho , Chi-Hsiang Sun
- 申请人: Winbond Electronics Corp.
- 申请人地址: TW Taichung City
- 专利权人: Winbond Electronics Corp.
- 当前专利权人: Winbond Electronics Corp.
- 当前专利权人地址: TW Taichung City
- 优先权: TW109129393 20200827
- 主分类号: H03L7/081
- IPC分类号: H03L7/081
摘要:
A control circuit of delay lock loop and a control method thereof are provided. The control circuit includes a power status detector, a voltage comparator, an enable signal generator and a control signal generator. The power status detector detects a transition edge of a clock enable signal to generate a trigger signal corresponding to a variation of an operation power. The voltage comparator compares the operation power with a reference voltage to generate a comparison result. The enable signal generator sets an enable signal to an active state according to the trigger signal and sets the enable signal to a non-active state according to the comparison result. The control signal generator outputs a control clock to generate a control signal when the enable signal is in the active state.
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