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公开(公告)号：US11411555B2
公开(公告)日：2022-08-09
申请号：US17395353
申请日：2021-08-05
申请人： Intel Corporation
发明人： Ee Wah Lim , Lay Leng Lim
摘要： Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-type networks in the PI mixer are decoupled, and DCC mechanism are blended in the PI mixer code decoding scheme to enable a low latency phase interpolation and duty cycle correction. The circuit comprises a first mixer circuitry controllable by a first code; a second mixer circuitry controllable by a second code; a node coupled to outputs of the first and second mixers; and a keeper circuitry coupled to the node, wherein the first and second mixers are tri-stable mixers.
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公开(公告)号：US11088682B2
公开(公告)日：2021-08-10
申请号：US16221392
申请日：2018-12-14
申请人： Intel Corporation
发明人： Ee Wah Lim , Lay Leng Lim
摘要： Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-type networks in the PI mixer are decoupled, and DCC mechanism are blended in the PI mixer code decoding scheme to enable a low latency phase interpolation and duty cycle correction. The circuit comprises a first mixer circuitry controllable by a first code; a second mixer circuitry controllable by a second code; a node coupled to outputs of the first and second mixers; and a keeper circuitry coupled to the node, wherein the first and second mixers are tri-stable mixers.
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公开(公告)号：US20210367588A1
公开(公告)日：2021-11-25
申请号：US17395353
申请日：2021-08-05
申请人： Intel Corporation
发明人： Ee Wah Lim , Lay Leng Lim
摘要： Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-type networks in the PI mixer are decoupled, and DCC mechanism are blended in the PI mixer code decoding scheme to enable a low latency phase interpolation and duty cycle correction. The circuit comprises a first mixer circuitry controllable by a first code; a second mixer circuitry controllable by a second code; a node coupled to outputs of the first and second mixers; and a keeper circuitry coupled to the node, wherein the first and second mixers are tri-stable mixers.
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