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公开(公告)号：US12206496B2
公开(公告)日：2025-01-21
申请号：US17356243
申请日：2021-06-23
Applicant: Intel Corporation
Inventor： Elan Banin , Lior Menashe , Eytan Mann , Ofir Degani , Rotem Banin
IPC: H04L1/00
Abstract: For example, an apparatus may include an encoder configured to encode data into a plurality of codewords according to a parity function for a transmission modulated according to a Differential Modulation (DM) scheme, and/or a decoder to decode received codewords of the transmission.
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公开(公告)号：US11902062B2
公开(公告)日：2024-02-13
申请号：US17754311
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Elan Banin , Rotem Banin , Ofir Degani , Eytan Mann
CPC classification number: H04L25/4902
Abstract: An apparatus for transmitting a bit in addition to a plurality of payload data symbols of a communication protocol is provided. The apparatus comprises an input interface configured to receive information about a bit value of the bit. Further, the apparatus comprises a transmission circuit configured to, if the bit value is a first value, transmit the plurality of payload data symbols at predetermined positions in a data signal as pulses of variable pulse length. The respective pulse length of each of the pulses is selected based on the symbol value of the payload data symbol represented by the respective pulse. If the bit value is a second value, the transmission circuit is configured to transmit a pulse exhibiting a pulse length being longer than a maximum payload data symbol pulse length defined in the communication protocol at the predetermined position of the pulse for the d-th payload data symbol of the plurality of payload data symbols, d=k+i if k+i≤z. d=([k+i] mod z) if k+i>z. k is the symbol value of the i-th payload data symbol of the plurality of payload data symbols, z is the number of possible symbol values of the payload data symbols defined in the communication protocol, and 1≤i≤z.
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公开(公告)号：US20230413195A1
公开(公告)日：2023-12-21
申请号：US17841907
申请日：2022-06-16
Applicant: Intel Corporation
Inventor： Evgeny Shumaker , Elan Banin , Ofir Degani
IPC: H04W56/00
CPC classification number: H04W56/001
Abstract: A radio-head apparatus can comprise memory to store dithering information of the apparatus. The radio-head can further include radio-head circuitry to generate a clock signal according to the dithering information and to provide a wakeup signal, subsequent to commencement of clock signal generation, to instruct a secondary RH to use the clock signal of the RH. The same wakeup signal is also used to synchronize the finite state machines of both RHs that govern and report the dithering information. Synchronization of the FSM allows estimation of information to be used in the secondary RH for compensation of the clock dithering applied in the primary RH. Other systems and apparatuses are described.
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4.发明公开公开(公告)号：US20230318643A1
公开(公告)日：2023-10-05
申请号：US17710861
申请日：2022-03-31
Applicant: Intel Corporation
Inventor： Elan Banin , Assaf Ben-Bassat , Ashoke Ravi , Rotem Banin , Ofir Degani
CPC classification number: H04B1/10 , H04B1/0028 , H04B1/005 , H04B1/68
Abstract: For example, a transmitter, e.g., for a wireless communication device, may be configured to transmit a wideband Radio Frequency (RF) Transmit (Tx) signal having a wide bandwidth of at least 80 Megahertz (MHz). For example, the transmitter may be configured to generate the wideband RF Tx signal having the wide bandwidth based on a baseband signal. The transmitter may be configured to generate the wideband RF Tx signal including a suppressed third harmonic and a suppressed fifth harmonic.
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公开(公告)号：US11387852B2
公开(公告)日：2022-07-12
申请号：US16639780
申请日：2018-09-17
Applicant: Intel Corporation
Inventor： Elan Banin , Eytan Mann , Rotem Banin , Ronen Gernizky , Ofir Degani , Igal Kushnir , Shahar Porat , Amir Rubin , Vladimir Volokitin , Elinor Kashani , Dmitry Felsenstein , Ayal Eshkoli , Tai Davidson , Eng Hun Ooi , Yossi Tsfati , Ran Shimon
Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20200212943A1
公开(公告)日：2020-07-02
申请号：US16639780
申请日：2018-09-17
Applicant: Intel Corporation
Inventor： Elan Banin , Eytan Mann , Rotem Banin , Ronen Gernizky , Ofir Degani , Igal Kushnir , Shahar Porat , Amir Rubin , Vladimir Volokitin , Elinor Kashani , Dmitry Felsenstein , Ayal Eshkoli , Tal Davidson , Eng Hun Ooi , Yossi Tsfati , Ran Shimon
Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.
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7.发明授权公开(公告)号：US09374197B2
公开(公告)日：2016-06-21
申请号：US14229803
申请日：2014-03-28
Applicant: Intel Corporation
Inventor： Moshe Teplitsky , Michael Genossar , Elan Banin
CPC classification number: H04L1/0045 , H04B1/30 , H04B2001/305 , H04W56/0035
Abstract: Logic for direct current (DC) estimation of a wireless communication packet. Logic may determine a first DC estimation based upon a first set of sequences in a preamble of the wireless communication packet. Logic may determine a second DC estimation based upon a second set of sequences in the preamble. Logic may select one of the DC estimations based upon a frequency-offset estimation. Logic may remove one of the DC estimations from the packet. Logic to null DC bins that result from a Fourier transform of the packet to mitigate transmitter DC bias. And logic to determine a correction for the packet based upon a difference between a predetermined guard interval value and a received guard interval value and to apply the correction to the packet.
Abstract translation: 用于无线通信分组的直流（DC）估计的逻辑。 逻辑可以基于无线通信分组的前导码中的第一组序列来确定第一DC估计。 逻辑可以基于前导码中的第二组序列来确定第二DC估计。 逻辑可以基于频率偏移估计来选择直流估计之一。 逻辑可以从分组中去除一个DC估计。 逻辑来清除由数据包的傅立叶变换产生的直流信道，以减轻发射机直流偏置。 以及用于基于预定保护间隔值和接收到的保护间隔值之间的差来确定对分组的校正并且将校正应用于分组的逻辑。
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公开(公告)号：US12101683B2
公开(公告)日：2024-09-24
申请号：US17129702
申请日：2020-12-21
Applicant: Intel Corporation
Inventor： Omer Sholev , Ofir Degani , Elan Banin , Uri Parker , Assaf Gurevitz
Abstract: Among other things, embodiments of the present disclosure help to overcome environment-specific dependency issues of conventional Wi-Fi-based sensing systems, thus allowing a neural network to make better proximity predictions in an unseen environment. Other embodiments may be described and claimed.
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公开(公告)号：US11991265B2
公开(公告)日：2024-05-21
申请号：US17481357
申请日：2021-09-22
Applicant: Intel Corporation
Inventor： Elan Banin , Evgeny Shumaker , Ofir Degani , Rotem Banin , Shahar Gross
IPC: H04L27/22 , H03C3/06 , H04B1/04 , H04L7/033 , H04L27/152
CPC classification number: H04L7/0331 , H03C3/06 , H04L7/0332 , H04L27/152 , H04L27/22
Abstract: A wireless communication device for asymmetrical frequency spreading including a processor configured to receive a frequency band message comprising a maximum difference and a minimum difference, wherein the maximum difference is between a maximum frequency of a sub-band and a signal frequency, and wherein the minimum difference is between the minimum frequency of the sub-band and the signal frequency compare the maximum difference and the minimum difference with each other; and generate a frequency shift based on the comparison.
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公开(公告)号：US11592339B2
公开(公告)日：2023-02-28
申请号：US16727966
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Omer Sholev , Elan Banin , Ofir Degani , Assaf Ben-Bassat
Abstract: A device may comprise: a storage for storing a reference output representing an output of an electrical circuit at a reference temperature; one or more processors, configured to: determine a temperature shift based on a comparison of an output of the electrical circuit sensed at a sensing temperature and the reference output; determine a plurality of coefficients of a model of the temperature shift, wherein the model implements one or more functions that associate the plurality of coefficients and a temperature with the temperature shift at the temperature.
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