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    Programmable application specific integrated circuit and logic cell
    92.
    发明授权
    Programmable application specific integrated circuit and logic cell 失效
    可编程专用集成电路和逻辑单元

    公开(公告)号：US6078191A

    公开(公告)日：2000-06-20

    申请号：US38728

    申请日：1998-03-10

    Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

    Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

    IPC: H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

    CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

    Abstract translation: 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的逻辑单元。 逻辑单元包括四个双输入与门，两个六输入与门，三个多路复用器和延迟触发器。 逻辑单元是一种强大的通用逻辑构建块，适用于实现大多数TTL和门阵列宏图程序功能。 相当多种功能可以通过一个单元延迟来实现，包括宽达十三个输入的组合逻辑功能，最多三个输入的所有布尔传递函数，以及顺序触发器功能，如T，JK和带进位的计数。

    Programmable logic device with multi-level power control
    95.
    发明授权
    Programmable logic device with multi-level power control 失效
    具有多级功率控制的可编程逻辑器件

    公开(公告)号：US5751164A

    公开(公告)日：1998-05-12

    申请号：US668896

    申请日：1996-06-24

    Applicant: Bradley A. Sharpe-Geisler ,  Bryon I. Moyer

    Inventor： Bradley A. Sharpe-Geisler ,  Bryon I. Moyer

    IPC: H03K19/177 ,  H03K17/14

    CPC classification number: H03K19/17784 ,  H03K19/17704 ,  H03K19/17792

    Abstract: For each programmable logic block in a programmable logic device, a programmable power and speed control circuit is programmably configurable to generate an output signal on a power and speed control line so that the static power consumption of the corresponding programmable logic block is adjusted to provide a particular combination of power and speed for that programmable logic block, i.e., a specific power/speed performance point. For each programmable logic block in the programmable logic device, a plurality of programmable selectable speed/power levels are provided by the programmable power and speed control circuit. This allows a distribution of programmable logic blocks in the programmable logic device that are powered to various performance levels to match more closely a distribution of performance requirements by the circuit that includes the various programmable logic blocks.

    Abstract translation: 对于可编程逻辑器件中的每个可编程逻辑块，可编程功率和速度控制电路可编程配置为在功率和速度控制线上产生输出信号，使得相应的可编程逻辑块的静态功耗被调整以提供 该可编程逻辑块的功率和速度的特定组合，即特定的功率/速度性能点。 对于可编程逻辑器件中的每个可编程逻辑块，可编程功率和速度控制电路提供多个可编程可选速度/功率电平。 这允许可编程逻辑器件中的可编程逻辑块的分布被供电到各种性能水平，以更紧密地匹配包括各种可编程逻辑块的电路的性能要求的分布。

    Programmable application specific integrated circuit using logic circuits to program antifuses therein
    96.
    发明授权
    Programmable application specific integrated circuit using logic circuits to program antifuses therein 失效
    可编程应用专用集成电路，使用逻辑电路在其中编程反熔丝

    公开(公告)号：US5477167A

    公开(公告)日：1995-12-19

    申请号：US379061

    申请日：1995-01-27

    Applicant: Hua-Thye Chua

    Inventor： Hua-Thye Chua

    IPC: G11C17/18 ,  H03K19/177

    CPC classification number: H03K19/17776 ,  G11C17/18 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1778 ,  H03K19/17792

    Abstract: A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.

    Abstract translation: 随着处理技术的进步，可编程ASIC架构允许与设备的其他部分一起减少编程晶体管的尺寸。 编程使能电路用于允许在反熔丝的编程中使用具有较少位的编程地址移位寄存器。 公开了同时编程多个对应的反熔丝以加速ASIC编程的方法。 架构方面允许消除模块中的数字逻辑元件的输出保护，要消除一些测试晶体管，要降低其他测试晶体管的尺寸，减少互连线段上的电容，要消除的一些编程晶体管， 并减小其他编程晶体管的尺寸。

    EPLD chip with hybrid architecture optimized for both speed and flexibility
    97.
    发明授权
    EPLD chip with hybrid architecture optimized for both speed and flexibility 失效
    具有针对速度和灵活性优化的混合架构的EPLD芯片

    公开(公告)号：US5450021A

    公开(公告)日：1995-09-12

    申请号：US234097

    申请日：1994-04-28

    Applicant: David Chiang

    Inventor： David Chiang

    IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/177

    CPC classification number: H03K19/17792 ,  H03K19/018507 ,  H03K19/09429 ,  H03K19/17704

    Abstract: A hybrid EPLD (chip) architecture has multiple first blocks each including a first type programmable AND array and multiple first type macrocells which are complex in structure and highly configurable; and multiple blocks each including a second type programmable AND array having fewer input lines and product term output lines than does the first type AND array, and multiple second type macrocells which have fewer logic gates than do the first type macrocells. The EPLD has a programmable interconnect matrix for interconnecting all the blocks.

    Abstract translation: 混合EPLD（芯片）架构具有多个第一块，每个第一块包括第一类型可编程AND阵列和多个第一类型的宏单元，其结构复杂且高度可配置; 以及多个块，每个包括具有比第一类型AND阵列少的输入线和产品项输出线的第二类型可编程AND阵列，以及具有比第一类宏单元更少的逻辑门的多个第二类型宏单元。 EPLD具有用于互连所有块的可编程互连矩阵。

    EPLD chip with hybrid architecture optimized for both speed and flexibility
    99.
    发明授权
    EPLD chip with hybrid architecture optimized for both speed and flexibility 失效
    具有针对速度和灵活性优化的混合架构的EPLD芯片

    公开(公告)号：US5362999A

    公开(公告)日：1994-11-08

    申请号：US32920

    申请日：1993-03-18

    Applicant: David Chiang

    Inventor： David Chiang

    IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/177

    CPC classification number: H03K19/17792 ,  H03K19/018507 ,  H03K19/09429 ,  H03K19/17704

    Abstract: A hybrid EPLD (chip) architecture has multiple first blocks each including a first type programmable AND array and multiple first type macrocells which are complex in structure and highly configurable; and multiple blocks each including a second type programmable AND array having fewer input lines and product term output lines than does the first type AND array, and multiple second type macrocells which have fewer logic gates than do the first type macrocells. The EPLD has a programmable interconnect matrix for interconnecting all the blocks.

    Abstract translation: 混合EPLD（芯片）架构具有多个第一块，每个第一块包括第一类型可编程AND阵列和多个第一类型的宏单元，其结构复杂且高度可配置; 以及多个块，每个包括具有比第一类型AND阵列少的输入线和产品项输出线的第二类型可编程AND阵列，以及具有比第一类宏单元更少的逻辑门的多个第二类型宏单元。 EPLD具有用于互连所有块的可编程互连矩阵。

    Programmable logic device
    100.
    再颁专利
    Programmable logic device 失效
    可编程逻辑器件

    公开(公告)号：USRE34444E

    公开(公告)日：1993-11-16

    申请号：US725353

    申请日：1991-07-03

    Applicant: Cecil H. Kaplinsky

    Inventor： Cecil H. Kaplinsky

    IPC: H03K19/177 ,  H04Q3/52 ,  H04Q1/00

    CPC classification number: H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17792 ,  H04Q3/521

    Abstract: A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input pins can be programmably connected to any input of any functional unit, and the outputs of functional units can be programmably connected to any input of any functional unit or any output pin. The interconnection matrices may be a simple array of crossing conductive lines with crossings connected by fuses, EPROM, or EEPROM switches or may have additional series switches to limit the effective impedance so as to speed propagation through these matrices. A fast path through one functional unit bypassing the interconnection matrices is available for a limited number of input and output pins. Multiplexers and other structures may be provided at ends of the fixed conductive lines to enable exhaustive testing of individual functional units, interconnections and logic, and structure may also be provided for on-chip monitoring of state information and providing the information to the external world when certain preselected events happen.

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