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    System and method for optimizing routing lines in a programmable logic device
    3.
    发明授权
    System and method for optimizing routing lines in a programmable logic device 有权
    用于优化可编程逻辑器件中路由线路的系统和方法

    公开(公告)号：US06895570B2

    公开(公告)日：2005-05-17

    申请号：US10057232

    申请日：2002-01-25

    Applicant: David M. Lewis ,  Vaughn Betz ,  Paul Leventis ,  Michael Chan ,  Cameron R. McClintock ,  Andy L. Lee ,  Christopher F. Lane ,  Srinivas T. Reddy ,  Richard Cliff

    Inventor： David M. Lewis ,  Vaughn Betz ,  Paul Leventis ,  Michael Chan ,  Cameron R. McClintock ,  Andy L. Lee ,  Christopher F. Lane ,  Srinivas T. Reddy ,  Richard Cliff

    IPC: G06F17/50 ,  H01L21/82 ,  H03K19/177

    CPC classification number: H03K19/17736 ,  G06F17/5054 ,  G06F17/5077

    Abstract: An embodiment of this invention pertains to a wire that interconnects multiple function blocks within a programmable logic device (“PLD”). An electrically optimum physical length is determined for the wire. A wire having the electrically optimum physical length transmits a signal down the wire as fast as possible. Some of the wires used in the PLD have a physical length substantially the same as the electrically optimum physical length or an adjustment of the electrically optimum physical length to account for non-electrical considerations. The physical length, as used herein, is the measured length of the wire. A logical length of the wire, as used herein, is the number of function blocks that the wire spans. Given that the function blocks have a different height and width, the logical length of the wire varies depending on the orientation of the wire.A routing architecture is an array that includes rows and columns of function blocks. The columns of the array are connected with horizontal lines (“H-line”) and the rows of the array are connected with vertical lines (“V-line). The types of H-lines include a H4 line that spans four function blocks, a H8 line that spans eight function blocks, and a H24 line that spans twenty-four function blocks. The types of V-lines include a V4 line that spans four function blocks, a V8 line that spans eight function blocks, and a V16 line that spans sixteen function blocks.

    Abstract translation: 本发明的实施例涉及将可编程逻辑器件（“PLD”）内的多个功能块互连的导线。 确定电线最佳物理长度。 具有最佳物理长度的导线尽可能快地将信号沿导线传送。 在PLD中使用的一些电线具有与电最佳物理长度基本相同的物理长度或电学最佳物理长度的调整以考虑非电学考虑。 如本文所使用的物理长度是测量的线的长度。 如本文所使用的，线的逻辑长度是导线跨越的功能块的数量。 假设功能块具有不同的高度和宽度，则线的逻辑长度根据线的方向而变化。 路由架构是包括功能块的行和列的数组。 数组的列与水平线（“H-line”）连接，阵列与垂直线（“V线”）连接，H线的类型包括四条功能块的H4线 ，一个跨越八个功能块的H8线，以及跨越二十四个功能块的H24线，V线的类型包括跨越四个功能块的V4线，跨越八个功能块的V8线，以及V16线 线跨越十六个功能块。

    Routing architecture for a programmable logic device
    4.
    发明授权
    Routing architecture for a programmable logic device 有权

    公开(公告)号：US06630842B1

    公开(公告)日：2003-10-07

    申请号：US10140287

    申请日：2002-05-06

    Applicant: David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

    Inventor： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

    IPC: H03K19177

    CPC classification number: H03K19/17736

    Abstract: An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides. In this configuration, the width of one of the first channel, the second channel, or the third channel differs from the width of another one of those channels. Input multiplexers route signals from the wires of the channels to the inputs of the function block. Output multiplexers and drivers drive the outputs of the function block through the wires of the channels. By placing the input multiplexers and the output multiplexers in certain relative arrangements, the logical distance that an output signal from the function block can travel on a wire is increased and that signal can be looped back to itself. In addition, each of the inputs and the outputs of the function block can be connected to both horizontal and vertical channels, and an output of the function block can be directly connected to an input of an adjacent function block.

    Programmable logic device with redundant circuitry
    6.
    发明授权
    Programmable logic device with redundant circuitry 有权
    具有冗余电路的可编程逻辑器件

    公开(公告)号：US06344755B1

    公开(公告)日：2002-02-05

    申请号：US09691424

    申请日：2000-10-18

    Applicant: Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

    Inventor： Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

    IPC: H03K19003

    CPC classification number: H03K19/17764 ,  H03K19/17736

    Abstract: A programmable logic device is provided that allows a redundant row of programmable logic to be shifted into place to repair the device when a defect is detected in a row of programmable logic on the device. The redundant row is shifted into place by routing programming data into the normal logic and the redundant logic while bypassing the row of logic containing the defect. Switching circuitry may be used to direct programming data into the serial inputs of various data registers that are then used to load the programming data into the device. The patterns of programmable connections that are made between programmable logic regions on the device and vertical and horizontal conductors also allow redundant logic to be shifted into place. Some connections between the logic and the horizontal and vertical conductors may be identical within a column to facilitate shifting. Other connections may only partially overlap between respective rows. The partially overlapping pattern allows the connections to be less regular, which increases flexibility when routing signals on the device.

    Abstract translation: 提供了一种可编程逻辑器件，其允许在器件上的可编程逻辑行中检测到缺陷时将冗余的可编程逻辑行移位到位以修复器件。 通过将编程数据路由到正常逻辑和冗余逻辑中来绕过包含缺陷的逻辑行，将冗余行移位到位。 开关电路可用于将编程数据引导到各种数据寄存器的串行输入，然后将其用于将编程数据加载到器件中。 在设备上的可编程逻辑区域和垂直和水平导体之间进行的可编程连接的模式也允许将冗余逻辑移位到位。 逻辑和水平和垂直导体之间的一些连接可以在列内相同以便于移动。 其他连接可能仅在相应行之间部分重叠。 部分重叠的模式允许连接不太规则，这在设备上路由信号时增加灵活性。

    Redundancy circuitry for programmable logic devices with interleaved input circuits
    7.
    发明授权
    Redundancy circuitry for programmable logic devices with interleaved input circuits 有权
    具有交错输入电路的可编程逻辑器件的冗余电路

    公开(公告)号：US06337578B2

    公开(公告)日：2002-01-08

    申请号：US09795870

    申请日：2001-02-28

    Applicant: David E. Jefferson ,  Srinivas T. Reddy

    Inventor： David E. Jefferson ,  Srinivas T. Reddy

    IPC: H03K19173

    CPC classification number: H03K19/17764 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778

    Abstract: Redundant circuitry is provided for a programmable logic device that uses an interleaved input multiplexer circuit arrangement. The programmable logic device has at least one row of logic regions and has multiple columns, each of which contains one of the interleaved input multiplexers and one of the logic regions. A set of conductors associated with the row of logic regions is used to convey signals between the logic regions. Each interleaved logic region distributes logic signals from the conductors in the row to two adjacent logic regions. Bypass circuitry is provided in each column for bypassing the interleaved input multiplexer and logic region in that column. If a defect is detected in a column during testing of the device, the manufacturer can repair the device using the bypass circuitry to bypass that column. Spare logic is provided to replace the circuitry lost when a defective column is bypassed.

    Abstract translation: 为可编程逻辑器件提供冗余电路，该可编程逻辑器件使用交错输入多路复用器电路装置。 可编程逻辑器件具有至少一行逻辑区域，并且具有多个列，每个列包含交错输入多路复用器之一和逻辑区中的一个。 与逻辑区域行相关联的一组导体用于在逻辑区域之间传送信号。 每个交错逻辑区域将逻辑信号从行中的导体分配到两个相邻的逻辑区域。 在每列中提供旁路电路，以绕过该列中的交错输入多路复用器和逻辑区域。 如果在测试设备期间在列中检测到缺陷，制造商可以使用旁路电路修复设备以绕过该列。 提供备用逻辑来替代绕过故障列时丢失的电路。

    Fast signal conductor networks for programmable logic devices
    8.
    发明授权
    Fast signal conductor networks for programmable logic devices 有权
    用于可编程逻辑器件的快速信号导线网络

    公开(公告)号：US06225822B1

    公开(公告)日：2001-05-01

    申请号：US09287048

    申请日：1999-04-06

    Applicant: Christopher F. Lane ,  Srinivas T. Reddy

    Inventor： Christopher F. Lane ,  Srinivas T. Reddy

    IPC: H03K19177

    CPC classification number: H03K19/17736 ,  H03K19/17792

    Abstract: A programmable logic integrated circuit device has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. A so-called “fast conductor” network is provided on the device for rapidly and efficiently distributing a relatively small number of signals to substantially any logic area on the device. The fast conductor network has several main conductors that substantially bisect the array in one direction (e.g., by extending parallel to the column axis). Some main conductors can carry signals from off the device. Other main conductors can carry signals generated on the device. The network further includes secondary conductors that extend transverse to the main conductors (e.g., along each row of logic areas). Programmable logic connectors are provided for selectively applying signals from the main conductors to the secondary conductors and from the secondary conductors to the logic areas.

    Abstract translation: 可编程逻辑集成电路器件具有多个可编程逻辑区域，该可编程逻辑区域以这种区域的交叉行和列的二维阵列布置在器件上。 在设备上提供了所谓的“快速导体”网络，用于将相对较少数量的信号快速有效地分配到设备上的基本上任何逻辑区域。 快速导体网络具有几个主导体，其在一个方向上基本上平分阵列（例如，通过平行于列轴线延伸）。 一些主导体可以携带离开设备的信号。 其他主导体可以携带在设备上产生的信号。 网络还包括横向于主导体（例如，沿着每一排逻辑区域）延伸的次级导体。 提供可编程逻辑连接器，用于选择性地将信号从主导体施加到次级导体，并从次导体到逻辑区域。

    Techniques for programming programmable logic array devices
    9.
    发明授权
    Techniques for programming programmable logic array devices 失效
    用于编程可编程逻辑阵列器件的技术

    公开(公告)号：US06191608B1

    公开(公告)日：2001-02-20

    申请号：US08851250

    申请日：1997-05-05

    Applicant: Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard Shaw Terrill ,  Rina Raman ,  Robert Richard Noel Bielby

    Inventor： Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard Shaw Terrill ,  Rina Raman ,  Robert Richard Noel Bielby

    IPC: H03K19177

    CPC classification number: H03K19/17776 ,  G06F17/5054 ,  H03K19/1774 ,  H03K19/17748

    Abstract: Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

    Abstract translation: 可编程逻辑阵列器件由网络中的编程设备编程，这些器件可以利用任何大小或复杂度的程序来编程任何数量的这种逻辑器件。 编程数据和控制的源可以是微处理器或一个或多个串行EPROM，一个EPROM配备有时钟电路。 可以使用几个并行数据流来加速编程操作。 可以提供具有可编程可变速度的时钟电路以便于具有不同速度特性的编程逻辑器件。 编程协议可以包括在每个编程数据传输之后从逻辑设备到编程数据源的确认，使得源可以以逻辑设备能够接受该数据的速度自动发送编程数据。

    Programmable logic array integrated circuit devices
    10.
    发明授权
    Programmable logic array integrated circuit devices 失效
    可编程逻辑阵列集成电路器件

    公开(公告)号：US5986470A

    公开(公告)日：1999-11-16

    申请号：US970830

    申请日：1997-11-14

    Applicant: Richard G. Cliff ,  Srinivas T. Reddy ,  Rina Raman ,  L. Todd Cope ,  Joseph Huang ,  Bruce B. Pedersen

    Inventor： Richard G. Cliff ,  Srinivas T. Reddy ,  Rina Raman ,  L. Todd Cope ,  Joseph Huang ,  Bruce B. Pedersen

    IPC: H03K19/173 ,  H03K19/177

    CPC classification number: H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

    Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

    Abstract translation: 可编程逻辑阵列集成电路器件包括以有意义的行和列的二维阵列布置在器件上的多个可编程逻辑区域。 互连导体与每行和列相关联。 与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。 为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。 逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。 还提供了许多其他增强功能。

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