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公开(公告)号：US20220247394A1
公开(公告)日：2022-08-04
申请号：US17162440
申请日：2021-01-29
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Yu-Der Chih
IPC: H03K3/356
Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.
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公开(公告)号：US20220238155A1
公开(公告)日：2022-07-28
申请号：US17721985
申请日：2022-04-15
Inventor： Chien-An Lai , Chung-Cheng Chou , Yu-Der Chih
Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
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公开(公告)号：US11367468B1
公开(公告)日：2022-06-21
申请号：US17186250
申请日：2021-02-26
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Yu-Der Chih
Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.
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公开(公告)号：US20220114046A1
公开(公告)日：2022-04-14
申请号：US17556101
申请日：2021-12-20
Inventor： Hiroki Noguchi , Yu-Der Chih , Hsueh-Chih Yang , Randy Osborne , Win-San Khwa
Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.
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公开(公告)号：US11276469B2
公开(公告)日：2022-03-15
申请号：US16901200
申请日：2020-06-15
Inventor： Yu-Der Chih
Abstract: A memory device is provided. The memory device includes a first transistor and a second transistor connected in series with the first transistor. The second transistor is programmable between a first state and a second state. A bit line connected to the second transistor. A sense amplifier connected to the bit line. The sense amplifier is operative to sense data from the bit line. A feedback circuit connected to the sense amplifier, wherein the feedback circuit is operative to control a bit line current of the bit-line.
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Patent Agency Ranking
公开(公告)号：US11250908B2
公开(公告)日：2022-02-15
申请号：US16544309
申请日：2019-08-19
Inventor： Yu-Der Chih , Chia-Fu Lee , Yi-Chun Shih , Hon-Jarn Lin , Ku-Feng Lin
Abstract: A method for sensing logical states of memory cells in multiple segments in a memory device, each cell having a high- and low-resistance state, resulting in different cell current levels for the different resistance states. The method includes determining target reference current levels for the respective segments, at least two of the target reference current levels being different from each other; generating a reference current for each segment with the target reference current level for that segment; comparing the cell current level for each cell to the reference current level for the segment the cell is in; and determining the logical states of the memory cells based on the comparison.
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公开(公告)号：US11195562B2
公开(公告)日：2021-12-07
申请号：US16870220
申请日：2020-05-08
Inventor： Yi-Chun Shih , Chia-Fu Lee , Yu-Der Chih
Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
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公开(公告)号：US20210358532A1
公开(公告)日：2021-11-18
申请号：US17391639
申请日：2021-08-02
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Po-Hao Lee , Ku-Feng Lin , Yi-Chun Shih , Yu-Der Chih
Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
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99.发明申请公开(公告)号：US20210306148A1
公开(公告)日：2021-09-30
申请号：US17106856
申请日：2020-11-30
Inventor： Shih-Lien Linus Lu , Kun-hsi Li , Shih-Liang Wang , Jonathan Tsung-Yung Chang , Yu-Der Chih , Cheng-En Lee
Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
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公开(公告)号：US20210096963A1
公开(公告)日：2021-04-01
申请号：US17010058
申请日：2020-09-02
Inventor： Yu-Der Chih
Abstract: A system includes: a processor; a register configured to store a plurality of words, non-volatile memory having a plurality of cells, each cell corresponding to one of the words of the register, and wherein the each cell of the plurality of cells are set to an initial reset value; a first controller that in response to a loss in power: determines the word stored by the register; and changes the initial reset value of the cell of the non-volatile memory corresponding to the determined word stored by the register to a set value; a second controller that in response to detecting a restoration in power: identifies the cell having the set value; writes the word corresponding to the identified cell to the register; and resets the cells of the non-volatile memory to the initial reset value.
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