公开(公告)号：US20220352350A1

公开(公告)日：2022-11-03

申请号：US17869028

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jin-Mu Yin ,  Wei-Yang Lee ,  Chih-Hao Yu ,  Yen-Ting Chen ,  Chia-Pin Lin

IPC分类号： H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/423

摘要： The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features.

公开(公告)号：US20220328661A1

公开(公告)日：2022-10-13

申请号：US17838649

申请日：2022-06-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-Hsieh Wong ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/78

摘要： In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

公开(公告)号：US20220328648A1

公开(公告)日：2022-10-13

申请号：US17465259

申请日：2021-09-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-Hsieh Wong ,  Alex Lee ,  Wei-Han Fan ,  Tzu-Hua Chiu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/764 ,  H01L29/66

摘要： A semiconductor device includes a base portion on a semiconductor substrate, a channel layer vertically above the base portion and extending parallel to a top surface of the semiconductor substrate, a gate portion between the channel layer and the base portion, a source/drain feature connected to the channel layer, an inner spacer between the source/drain feature and the gate portion, and an air gap between the source/drain feature and the semiconductor substrate. Moreover, a bottom surface of the source/drain feature is exposed in the air gap.

公开(公告)号：US20220285561A1

公开(公告)日：2022-09-08

申请号：US17464500

申请日：2021-09-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Jen Lai ,  Wei-Yang Lee ,  De-Fang Chen ,  Ting-Wen Shih

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

摘要： A method includes providing a semiconductor structure including a fin protruding from a substrate, where the fin includes first semiconductor layers and second semiconductor layers, recessing the fin to form a source/drain (S/D) recess, forming an S/D feature in the S/D recess, trimming the S/D feature, depositing a dielectric layer to cover the S/D feature, forming a contact hole in the dielectric layer to expose the S/D feature, and forming a metal contact in the contact hole.

公开(公告)号：US20220238659A1

公开(公告)日：2022-07-28

申请号：US17159423

申请日：2021-01-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Ming Lee ,  Wei-Yang Lee

IPC分类号： H01L29/40 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/786 ,  H01L29/417

摘要： A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first dielectric layer around the dummy contract structure, performing a second deposition process to deposit an oxide layer on the first dielectric layer, removing the dummy contract structure to form a trench, depositing a sacrificial layer on sidewalls of the trench, depositing a second dielectric layer on the sacrificial layer, filling the trench with a conductive material, and removing the sacrificial layer to form an air spacer between the first dielectric layer and the second dielectric layer.

公开(公告)号：US20220093591A1

公开(公告)日：2022-03-24

申请号：US17027240

申请日：2020-09-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Feng-Ching Chu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234

摘要： An integrated circuit includes a stacked FinFET in a second area and a GAA transistor in a first area. The stacked FinFET includes two first source/drain, first and second semiconductor layers alternately stacked one over another and between the two first source/drain, a first gate dielectric layer over top and sidewalls of the first and second semiconductor layers, a first gate electrode layer over the first gate dielectric layer, and first spacer features laterally between the second semiconductor layers and the two first source/drain. The first and the second semiconductor layers include different materials. The GAA transistor includes two second source/drain, third semiconductor layers electrically connecting the two second source/drain, a second gate dielectric layer wrapping around the third semiconductor layers, a second gate electrode over the second gate dielectric layer, and second spacer features laterally between the second gate dielectric layer and the two second source/drain.

公开(公告)号：US11257928B2

公开(公告)日：2022-02-22

申请号：US16682305

申请日：2019-11-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/8238

摘要： A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region. Each of the plurality of buffer layers may have an average thickness in a range of about 2 Å to about 30 Å.

公开(公告)号：US20210193534A1

公开(公告)日：2021-06-24

申请号：US16723218

申请日：2019-12-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L21/8238 ,  H01L21/311 ,  H01L21/768 ,  H01L29/08 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092

摘要： A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.

公开(公告)号：US20200176591A1

公开(公告)日：2020-06-04

申请号：US16382860

申请日：2019-04-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-Hsieh Wong ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/78

摘要： In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

公开(公告)号：US20190198646A1

公开(公告)日：2019-06-27

申请号：US16222583

申请日：2018-12-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Yang Lee ,  Chih-Shan Chen

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L27/088 ,  H01L29/165

CPC分类号： H01L29/66795 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.