Technique for non-destructive metal delamination monitoring in semiconductor devices
    91.
    发明授权
    Technique for non-destructive metal delamination monitoring in semiconductor devices 有权
    半导体器件中非破坏性金属分层监测技术

    公开(公告)号:US07638424B2

    公开(公告)日:2009-12-29

    申请号:US11536730

    申请日:2006-09-29

    Abstract: By providing large area metal plates in combination with respective peripheral areas of increased adhesion characteristics, delamination events may be effectively monitored substantially without negatively affecting the overall performance of the semiconductor device during processing and operation. In some illustrative embodiments, dummy vias may be provided at the periphery of a large area metal plate, thereby allowing delamination in the central area while substantially avoiding a complete delamination of the metal plate. Consequently, valuable information with respect to mechanical characteristics of the metallization layer as well as process flow parameters may be efficiently monitored.

    Abstract translation: 通过提供大面积金属板与相应的周边区域结合增加的粘合特性,可以有效地监测分层事件,而不会在加工和操作过程中不影响半导体器件的整体性能。 在一些示例性实施例中,可以在大面积金属板的周边设置虚拟通孔,从而允许中心区域分层,同时基本避免金属板的完全分层。 因此,可以有效地监测关于金属化层的机械特性以及工艺流程参数的有价值的信息。

    SUBSTRATE CONTACT FOR ADVANCED SOI DEVICES BASED ON A DEEP TRENCH CAPACITOR CONFIGURATION
    93.
    发明申请
    SUBSTRATE CONTACT FOR ADVANCED SOI DEVICES BASED ON A DEEP TRENCH CAPACITOR CONFIGURATION 有权
    基于深层电容电容配置的高级SOI器件的衬底接触

    公开(公告)号:US20090194844A1

    公开(公告)日:2009-08-06

    申请号:US12171633

    申请日:2008-07-11

    Applicant: Ralf Richter

    Inventor: Ralf Richter

    CPC classification number: H01L21/84 H01L21/743 H01L27/1087 H01L27/1203

    Abstract: By forming a first portion of a substrate contact in an SOI device on the basis of a trench capacitor process, the overall manufacturing process for patterning contact elements may be enhanced since the contacts may only have to extend down to the level of the semiconductor layer. Since the lower portion of the substrate contact may be formed concurrently with the fabrication of trench capacitors, complex patterning steps may be avoided which may otherwise have to be introduced when the substrate contacts are to be formed separately from contact elements connecting to the device level.

    Abstract translation: 通过基于沟槽电容器工艺在SOI器件中形成衬底接触的第一部分,可以增强用于对接触元件进行图形化的整体制造工艺,因为接触可能只能向下延伸到半导体层的水平。 由于衬底接触的下部可以与沟槽电容器的制造同时形成,所以可以避免复杂的图案化步骤,否则当衬底触点与连接到器件级别的接触元件分开形成时可能需要引入。

    TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL
    94.
    发明申请
    TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL 有权
    用于补偿中间层介质材料中沉积行为差异的技术

    公开(公告)号:US20090087999A1

    公开(公告)日:2009-04-02

    申请号:US12168443

    申请日:2008-07-07

    Abstract: By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

    Abstract translation: 通过选择性地提供具有适当厚度的缓冲层,在形成先进的半导体器件的层间电介质叠层的过程中,可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料,或者可以在沉积一种类型的电介质材料之后提供缓冲材料,并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。

    SEMICONDUCTOR DEVICE HAVING A GRAIN ORIENTATION LAYER
    95.
    发明申请
    SEMICONDUCTOR DEVICE HAVING A GRAIN ORIENTATION LAYER 有权
    具有谷物定向层的半导体器件

    公开(公告)号:US20090035936A1

    公开(公告)日:2009-02-05

    申请号:US12035518

    申请日:2008-02-22

    Abstract: A manufacturing process of a semiconductor device includes generating a less random grain orientation distribution in metal features of a semiconductor device by employing a grain orientation layer. The less random grain orientation, e.g., a grain orientation distribution which has a higher percentage of grains that have a predetermined grain orientation, may lead to improved reliability of the metal features. The grain orientation layer may be deposited on the metal features wherein the desired grain structure of the metal features may be obtained by a subsequent annealing process, during which the metal feature is in contact with the grain orientation layer.

    Abstract translation: 半导体器件的制造工艺包括通过采用晶粒取向层在半导体器件的金属特征中产生较少的随机晶粒取向分布。 随机晶粒取向较少,例如晶粒取向分布具有较高百分比的具有预定晶粒取向的晶粒,可能导致金属特征提高的可靠性。 晶粒取向层可以沉积在金属特征上,其中金属特征的期望晶粒结构可以通过随后的退火过程获得,在此期间金属特征与晶粒取向层接触。

    TECHNIQUE FOR PATTERNING DIFFERENTLY STRESSED LAYERS FORMED ABOVE TRANSISTORS BY ENHANCED ETCH CONTROL STRATEGIES
    96.
    发明申请
    TECHNIQUE FOR PATTERNING DIFFERENTLY STRESSED LAYERS FORMED ABOVE TRANSISTORS BY ENHANCED ETCH CONTROL STRATEGIES 有权
    通过增强蚀刻控制策略形成上述晶体管上的不同应力层的技术

    公开(公告)号:US20080206905A1

    公开(公告)日:2008-08-28

    申请号:US11868789

    申请日:2007-10-08

    Abstract: During the patterning of stressed layers having different types of intrinsic stress, the effects of the deposition of a silicon dioxide based etch indicator material between the first and second dielectric layers may be significantly reduced by a controlled etch on the basis of optical measurement data indicating the etch rate and, thus, the performance of the respective etch process. In other cases, highly efficient etch indicator species may be incorporated into the stressed dielectric layers or may be formed on a surface portion thereof with reduced layer thickness, thereby providing an enhanced endpoint detection signal without creating the negative effects of silicon dioxide based indicator layers. In one illustrative embodiment, a stressed silicon, nitrogen and carbon-containing layer may be combined with a stressed silicon and nitrogen-containing layer, wherein the carbon species provides a prominent endpoint detection signal.

    Abstract translation: 在具有不同类型的固有应力的应力层的图案化期间,可以通过基于表示第二和第二电介质层的光学测量数据的受控蚀刻来显着地减少基于二氧化硅的蚀刻指示剂材料沉积的影响 蚀刻速率,因此,各个蚀刻工艺的性能。 在其他情况下,可以将高效的蚀刻指示剂物质结合到应力介电层中,或者可以在其表面部分上形成具有减小的层厚度,从而提供增强的端点检测信号,而不产生基于二氧化硅的指示剂层的负面影响。 在一个说明性实施例中,应力硅,氮和碳的层可以与应力硅和含氮层组合,其中碳类提供突出的端点检测信号。

    Highly branched polyamide graft copolymers
    99.
    发明授权
    Highly branched polyamide graft copolymers 有权
    高分支聚酰胺接枝共聚物

    公开(公告)号:US06391982B1

    公开(公告)日:2002-05-21

    申请号:US09605874

    申请日:2000-06-29

    CPC classification number: C08G69/26 C08G69/02 C08G69/48 Y10S424/16

    Abstract: A graft copolymer is prepared by a process comprising: graft polymerizing a polyamide-forming monomer selected from the group consisting of lactams and &ohgr;-aminocarboxylic acids and an oligocarboxylic acid selected from the group consisting of from 0.015 to about 3 mol. % of dicarboxylic acid and from 0.01 to about 1.2 mol. % of tricarboxylic acid, in each case the stated amounts of oligocarboxylic acid based on a molar amount of lactam, &ohgr;-aminocarboxylic acid or combination thereof, onto from 0.5 to 25% by weight, based on the graft copolymer, of a polyamine having at least 11 nitrogen atoms and a number-average molecular weight Mn of at least 500 g/mol., wherein the amino group concentration in the graft copolymer ranges from 100 to 2500 mmol./kg.

    Abstract translation: 接枝共聚物通过以下方法制备,该方法包括:将选自内酰胺和ω-氨基羧酸的聚酰胺形成单体和选自0.015至约3mol的寡羧酸接枝聚合。 %的二羧酸和0.01至约1.2mol。 %的三羧酸,在每种情况下,所述量的基于内酰胺,ω-氨基羧酸或其组合的摩尔量的寡羧酸的量为基于接枝共聚物的0.5至25重量%的多胺,其具有 至少11个氮原子和数均分子量Mn为至少500g / mol,其中接枝共聚物中的氨基浓度范围为100-2500mmol / kg。

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