公开(公告)号：US20240355712A1

公开(公告)日：2024-10-24

申请号：US18303072

申请日：2023-04-19

Applicant: QUALCOMM Incorporated

Inventor： Michelle Yejin Kim ,  Hong Bok We ,  Joan Rey Villarba Buot ,  Kuiwon Kang

IPC: H01L23/488 ,  H01L21/48 ,  H01L23/14

CPC classification number: H01L23/488 ,  H01L21/486 ,  H01L23/142 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H10B80/00

Abstract: A substrate(s) for an integrated circuit (IC) package employing a metal core for improved electrical shielding and structural strength. In one aspect, a substrate comprises a core layer. The core layer comprises a metal core, the metal core having a first surface and a second surface opposite the first surface. The core layer further comprises a first insulation layer on the first surface and a second insulation layer on the second surface. The substrate further comprises a first metallization structure adjacent to the first insulation layer and a second metallization structure adjacent to the second insulation layer. The metal core provides electrical shielding of signals/power routed through the metal core for noise coupling reduction allowing a higher density of signal and power paths to be supported in substrate, while also strengthening structural integrity to prevent or reduce warpage in the IC package.

公开(公告)号：US20240332146A1

公开(公告)日：2024-10-03

申请号：US18193295

申请日：2023-03-30

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Hong Bok We ,  Zhijie Wang ,  Sang-Jae Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/42 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L24/83 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/83

Abstract: Integrated circuit (IC) package employing metal posts thermally coupling a die to an interposer substrate for dissipating thermal energy of the die are disclosed. In one aspect, the IC package includes a metal post(s) thermally coupled to the die. The metal post(s) is attached to metal interconnect(s) (e.g., metal trace, metal pad, metal line, metal plate) in the interposer substrate. In this manner, as thermal energy is generated in the die, this thermal energy dissipates through the metal post(s) and through the coupled metal interconnect(s) into the interposer substrate. Thus, metal interconnects, which are an available feature in an interposer substrate fabrication process, are deployed to form the foundation upon which metal posts are fabricated and thermally coupled to the die to provide heat dissipation for the die in the IC package.

公开(公告)号：US11832391B2

公开(公告)日：2023-11-28

申请号：US17038173

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Joan Rey Villarba Buot

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H05K1/181 ,  H05K3/303 ,  H05K2201/10522

Abstract: Terminal connection routing on top of a substrate surface connects to component terminals to and from PMIC devices and provides a novel structure to connect surface mount technology (SMT) passive device terminals on an SMT layer (such as a Cu bar mesh) that uses the 3D space available near to components to lower resistance/lower inductive path and provides a shorter path, SIP form factor reduction, a component placement density increase, creates an additional PDN layer for connectivity and, if the routing is encapsulated in a mold, protects the metal in the connection from oxidation. Methods are presented for providing a substrate, attaching a first device to a first surface of the substrate near a center of the substrate, attaching a second device to the first surface of the substrate near an edge of the substrate, and connecting a connection located on the first surface of the substrate between the first device and the second device.

公开(公告)号：US11823983B2

公开(公告)日：2023-11-21

申请号：US17210314

申请日：2021-03-23

Applicant: QUALCOMM Incorporated

Inventor： Kun Fang ,  Jaehyun Yeon ,  Suhyung Hwang ,  Hong Bok We

IPC: H01L23/482 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/482 ,  H01L23/528 ,  H01L23/5226

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate comprises at least one dielectric layer; a plurality of interconnects comprising plurality of pad-on-pad interconnects, wherein the plurality of pad-on-pad interconnects is embedded through a first surface of the substrate. The plurality of pad-on-pad interconnects includes a first pad-on-pad interconnect comprising a first pad and a second pad coupled to the first pad. The package further comprising a solder resist layer located over the first surface of the substrate. The solder resist layer comprises a first solder resist layer portion comprising a first thickness; and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The second solder resist layer portion is located between the at least one dielectric layer and the integrated device.

公开(公告)号：US20230307336A1

公开(公告)日：2023-09-28

申请号：US17656477

申请日：2022-03-25

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba Buot ,  Zhijie Wang ,  Aniket Patil ,  Hong Bok We

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49894 ,  H01L21/4857

Abstract: Package substrates employing a pad metallization layer for increased signal routing capacity, and related integrated circuit (IC) packages and fabrication methods. To support increased signal routing density in an IC package while mitigating an increase in overall IC package thickness, an outer metallization layer of the package substrate is provided as a thinner, pad metallization layer. A metal layer in the pad metallization layer includes metal pads for forming external connections to the package substrate. This allows an area in the adjacent metallization layer that would otherwise have larger width metal pads for forming external interconnects, to be used for other signal routing within the package substrate. This can increase the overall signal routing density of the package substrate while mitigating the increase in overall package substrate thickness if a full-sized additional metallization layer were added to the package substrate.

公开(公告)号：US11715688B2

公开(公告)日：2023-08-01

申请号：US16883829

申请日：2020-05-26

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We

IPC: H01L21/768 ,  H01L23/528 ,  H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L23/528 ,  H01L21/762 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/14 ,  H01L24/95 ,  H01L25/0657 ,  H01L29/0649 ,  H01L21/76835 ,  H05K2201/0187

Abstract: A package substrate has a dielectric layer and a redistribution metal layer. The dielectric layer has a first dielectric material and a second dielectric material. The first dielectric material is different than the second dielectric material. The second dielectric material may have a dielectric constant that is either greater than or less than the dielectric constant of the first dielectric material. The second dielectric may be selected based on a specific target application such as single-ended signal routing or serializer/deserializer (SERDES) routing.

公开(公告)号：US11581251B2

公开(公告)日：2023-02-14

申请号：US17093954

申请日：2020-11-10

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Zhijie Wang ,  Joan Rey Villarba Buot ,  Hong Bok We

IPC: H01L23/498 ,  H01L23/495 ,  H01L25/10 ,  H01L25/00

Abstract: A device comprising a first package and a second package coupled to the first package. The first package includes a first substrate, at least one gradient interconnect structure coupled to the first substrate, and a first integrated device coupled to the first substrate. The second package includes a second substrate and a second integrated device coupled to the second substrate. The second substrate is coupled to the at least one gradient interconnect structure.

公开(公告)号：US11545439B2

公开(公告)日：2023-01-03

申请号：US17017418

申请日：2020-09-10

Applicant: QUALCOMM Incorporated

Inventor： Aniket Patil ,  Hong Bok We ,  Kuiwon Kang

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L25/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00

Abstract: A package that includes a substrate and an integrated device. The substrate includes a core portion, a first substrate portion and a second substrate portion. The core portion includes a core layer and core interconnects. The first substrate portion is coupled to the core portion. The first substrate portion includes at least one first dielectric layer coupled to the core layer, and a first plurality of interconnects located in the at least one first dielectric layer. The second substrate portion is coupled to the core portion. The second substrate includes at least one second dielectric layer coupled to the core layer, and a second plurality of interconnects located in the at least one second dielectric layer. The core portion and the second substrate portion include a cavity. The integrated device is coupled to the first substrate portion through the cavity of the second substrate portion and the core portion.

公开(公告)号：US11258165B2

公开(公告)日：2022-02-22

申请号：US16236726

申请日：2018-12-31

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Chin-Kwan Kim ,  Jaehyun Yeon ,  Suhyung Hwang

IPC: H01Q1/38 ,  H01Q1/24 ,  H01Q9/12 ,  H01Q1/08 ,  H01Q5/364

Abstract: Certain aspects of the present disclosure provide an asymmetric antenna structure. An example antenna device generally includes a first antenna element, a second antenna element, and a flexible coupling element asymmetrically positioned between surfaces of the first and second antenna elements and electrically coupling the first antenna element to the second antenna element.

公开(公告)号：US20210407979A1

公开(公告)日：2021-12-30

申请号：US16910486

申请日：2020-06-24

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Marcus Hsu ,  Aniket Patil

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538

Abstract: Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other aspects, a compression bond is included between the IC dice mounted together in a back-to-back configuration to further minimize the overall height of the IC package.