公开(公告)号：US07479830B2

公开(公告)日：2009-01-20

申请号：US11648692

申请日：2007-01-03

Applicant: Songcheol Hong ,  Dong Ho Lee

Inventor： Songcheol Hong ,  Dong Ho Lee

IPC: H03F3/45 ,  H03F1/22

CPC classification number: H03F1/523 ,  H03F1/52 ,  H03F3/45179 ,  H03F3/45188 ,  H03F2203/45018 ,  H03F2203/45026 ,  H03F2203/45306 ,  H03F2203/45318 ,  H03F2203/45342 ,  H03F2203/45352

Abstract: Disclosed herein is a differential amplifier using body-source cross coupling. In a common gate differential amplifier in which common gate amplifiers are implemented in a differential structure, since the bodies of the common gate amplifiers are cross coupled to the sources of the opposite common gate amplifiers, it is possible to increase transconductance due to body effect to improve a gain. Since the potential of the body is equal to that of the source in a DC mode, a breakdown voltage reduction problem is alleviated.

Abstract translation: 这里公开了使用主体 - 交叉耦合的差分放大器。 在公共栅极放大器以差分结构实现的公共栅极差分放大器中，由于公共栅极放大器的主体与相对的公共栅极放大器的源极交叉耦合，所以可以增加由于体效应导致的跨导 改善收益。 由于身体的电位与直流模式的电位相等，所以降低了击穿电压的问题。

公开(公告)号：US07479408B2

公开(公告)日：2009-01-20

申请号：US11536611

申请日：2006-09-28

Applicant: Dong-Ho Lee

Inventor： Dong-Ho Lee

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/02

CPC classification number: H01L25/105 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/15311

Abstract: A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages.

Abstract translation: 通过堆叠至少两个区域阵列型芯片级封装件来制造本发明的堆叠封装。 相邻的一对芯片级封装的每个芯片级封装以上堆叠芯片级封装的焊盘焊盘与下堆叠芯片尺寸封装的方向相反的方式附接到另一芯片尺寸封装，并且电路 上堆叠芯片级封装的图案通过例如连接板电连接到下堆叠芯片级封装的图案。 因此，不仅可以堆叠扇出式芯片级封装，而且可以有效地堆叠普通区域阵列型芯片级封装。

公开(公告)号：US07457510B2

公开(公告)日：2008-11-25

申请号：US11727053

申请日：2007-03-23

Applicant: Dong Ho Lee ,  Won Ki Cho ,  Jae Myung Kim ,  Kyung Il Park

Inventor： Dong Ho Lee ,  Won Ki Cho ,  Jae Myung Kim ,  Kyung Il Park

IPC: G02B6/10 ,  F21V8/00

CPC classification number: G02B6/0038 ,  G02B6/0036 ,  G02B6/0053 ,  G02B6/0061

Abstract: A light guide member for guiding light may include a first pattern on a first side of the light guide member, the first pattern may include a plurality of first features extending along a first direction, and a plurality of second features extending along a second direction, wherein the first direction crosses the second direction, the first feature has a first feature size, the second feature has a second feature size, and the first feature size may be less than the second feature size.

公开(公告)号：US07450097B2

公开(公告)日：2008-11-11

申请号：US11144503

申请日：2005-06-03

Applicant: Keun-Shik Nah ,  Dong-Ho Lee

Inventor： Keun-Shik Nah ,  Dong-Ho Lee

IPC: G09G3/36

CPC classification number: G02F1/1345

Abstract: A liquid crystal display having a plurality of gate lines and a plurality of data lines extending in row and column directions, respectively, are formed on a panel. A switching device connected to the gate line and the data line and a pixel electrode connected thereto are provided in each of pixel areas partitioned by the gate lines and data lines. A data driving circuit and a data driving circuit are also provided on the panel, and apply voltages to the gate lines. A signal wire connected to the data driving circuit and including a plurality of color signal lines is provided on the panel and connects the data driving circuit to a signal controller of a printed circuit board. A pair of the plurality of color signal lines with differential relationship transmit color signals to the data driving circuit. A distance between the pair of the plurality of color signal lines is smaller than a width of each of the pair of the plurality of color signal lines and a distance between a pair of plurality of color signal lines without differential relationship. This relationship of the distances between the signal lines and the width thereof reduces the EMI noise.

Abstract translation: 在面板上形成具有多条栅极线和分别沿列和列方向延伸的多条数据线的液晶显示器。 连接到栅极线和数据线的开关器件和连接到其的像素电极设置在由栅极线和数据线分隔的每个像素区域中。 数据驱动电路和数据驱动电路也设置在面板上，并向栅极线施加电压。 连接到数据驱动电路并且包括多个彩色信号线的信号线被提供在面板上，并将数据驱动电路连接到印刷电路板的信号控制器。 具有差分关系的一对多个彩色信号线将彩色信号传输到数据驱动电路。 所述多个彩色信号线对之间的距离小于所述一对彩色信号线中的每一个的宽度和一对多个彩色信号线之间的距离，而没有差别关系。 信号线之间的距离与其宽度的这种关系降低了EMI噪声。

公开(公告)号：US20080261667A1

公开(公告)日：2008-10-23

申请号：US12104821

申请日：2008-04-17

Applicant: Dong Ho Lee ,  An-Sun Hyun ,  SungShin Kong

Inventor： Dong Ho Lee ,  An-Sun Hyun ,  SungShin Kong

IPC: H04M1/03

CPC classification number: H01Q1/243 ,  H01Q9/285

Abstract: A mobile terminal is provided that includes a first area having a first conductive surface, a second area having a second conductive surface, the second area separated from the first area, and a feeding point formed between the first conductive surface and the second conductive surface to supply electrical signals to or from the first and the second conductive surfaces. The first and the second conductive surfaces together from an internal antenna

Abstract translation: 提供了一种移动终端，其包括具有第一导电表面的第一区域，具有第二导电表面的第二区域，与第一区域分离的第二区域，以及形成在第一导电表面和第二导电表面之间的馈电点， 向第一和第二导电表面提供电信号。 第一和第二导电表面一起从内部天线

公开(公告)号：US20080251939A1

公开(公告)日：2008-10-16

申请号：US12100359

申请日：2008-04-09

Applicant: Hyun-Soo Chung ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Son-Kwan Hwang

Inventor： Hyun-Soo Chung ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Son-Kwan Hwang

IPC: H01L23/498

CPC classification number: H01L23/525 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/01049

Abstract: A chip stack package is provided, wherein semiconductor chips having different die sizes are stacked by arranging pads in a scribe region through a redistribution process, so that the thickness of the package can be reduced. A method of fabricating the chip stack package is also provided. In the chip stack package, a plurality of circuit patterns are arranged on one surface of a substrate, and a unit semiconductor chip is mounted thereon. The unit semiconductor chip includes a plurality of semiconductor chips sequentially stacked on the substrate. The semiconductor chips of the unit semiconductor chip have different die sizes. One of the semiconductor chips includes a plurality of first pads arranged in a first chip region, and the other semiconductor chips include second pads arranged in a scribe region at an outside of a second chip region defined by the scribe region.

Abstract translation: 提供了一种芯片堆叠封装，其中具有不同管芯尺寸的半导体芯片通过经由再分配工艺在划线区域中布置衬垫来堆叠，从而可以减小封装的厚度。 还提供了一种制造芯片堆叠封装的方法。 在芯片堆叠封装中，在基板的一个表面上布置多个电路图案，并且在其上安装单元半导体芯片。 单元半导体芯片包括顺序堆叠在基板上的多个半导体芯片。 单元半导体芯片的半导体芯片具有不同的管芯尺寸。 半导体芯片中的一个包括布置在第一芯片区域中的多个第一焊盘，并且其它半导体芯片包括布置在由划线区域限定的第二芯片区域的外侧的划线区域中的第二焊盘。

公开(公告)号：US20080169545A1

公开(公告)日：2008-07-17

申请号：US11790173

申请日：2007-04-24

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee ,  Myung-Kee Chung ,  Kang-Wook Lee ,  Sun-Won Kang ,  Keum-Hee Ma

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/90 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83856 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A stacked structure of semiconductor devices may include a plurality of stacked semiconductor devices, each having an upper surface and a lower surface and one or more via electrodes protruding from the upper surface to the lower surface. The via-electrodes may have upper parts (heads) protruding from the upper surface and lower parts (ends) protruding from the lower surface. The stacked semiconductor devices may be electrically connected to each other through the via-electrodes. A first adhesive film (e.g., patternable material) and a second adhesive film (e.g. puncturable material) may be formed between the stacked semiconductor devices. The stacked structure of semiconductor devices may be mounted on the upper surface of a printed circuit board (PCB) having a mount-specific adhesive film to form a semiconductor device package. The mounted stacked structure and the upper surface of the PCB may be further covered with a molding material.

Abstract translation: 半导体器件的层叠结构可以包括多个层叠的半导体器件，每个具有上表面和下表面以及从上表面到下表面突出的一个或多个通孔电极。 通孔电极可以具有从上表面突出的上部（头）和从下表面突出的下部（端部）。 层叠的半导体器件可以通过通孔电极彼此电连接。 可以在层叠的半导体器件之间形成第一粘合膜（例如，可图案化材料）和第二粘合膜（例如可刺穿材料）。 半导体器件的堆叠结构可以安装在具有安装专用粘合剂膜的印刷电路板（PCB）的上表面上以形成半导体器件封装。 安装的堆叠结构和PCB的上表面可以进一步被模制材料覆盖。

公开(公告)号：US20080164941A1

公开(公告)日：2008-07-10

申请号：US11964646

申请日：2007-12-26

Applicant: Chang-Ho Lee ,  Kyu Hwan An ,  Ki Seok Yang ,  Jaejoon Chang ,  Wangmyong Woo ,  Younsuk Kim ,  Haksun Kim ,  Ockgoo Lee ,  Dong Ho Lee ,  Hyungwook Kim ,  Joy Laskar

Inventor： Chang-Ho Lee ,  Kyu Hwan An ,  Ki Seok Yang ,  Jaejoon Chang ,  Wangmyong Woo ,  Younsuk Kim ,  Haksun Kim ,  Ockgoo Lee ,  Dong Ho Lee ,  Hyungwook Kim ,  Joy Laskar

IPC: H03F3/68 ,  H03F3/00

CPC classification number: H03F3/211 ,  H01F2017/0046 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/604 ,  H03F2200/451 ,  H03F2200/537 ,  H03F2200/541 ,  H03F2203/21139 ,  H03F2203/21157 ,  H03F2203/45704 ,  H03F2203/45706 ,  H03F2203/45731 ,  Y10T29/49071

Abstract: Systems and methods may be provided for a power amplifier system. The systems and methods may include a plurality of power amplifiers, where each power amplifier includes at least one output port. The systems and methods may also include a plurality of primary windings each having a first number of turns, where each primary winding is connected to at least one output port of the plurality of power amplifiers, and a single secondary winding inductively coupled to the plurality of primary windings, where the secondary winding includes a second number of turns greater than the first number of turns.

Abstract translation: 可以为功率放大器系统提供系统和方法。 系统和方法可以包括多个功率放大器，其中每个功率放大器包括至少一个输出端口。 系统和方法还可以包括多个初级绕组，每个初级绕组具有第一圈数，其中每个初级绕组连接到多个功率放大器的至少一个输出端口，以及感应耦合到多个 初级绕组，其中次级绕组包括大于第一匝数的第二匝数。

公开(公告)号：US20080160748A1

公开(公告)日：2008-07-03

申请号：US11954673

申请日：2007-12-12

Applicant: Kwon Hong ,  Dong Ho Lee ,  Jae Mun Kim ,  Hee Soo Kim ,  Jae Hyoung Koo

Inventor： Kwon Hong ,  Dong Ho Lee ,  Jae Mun Kim ,  Hee Soo Kim ,  Jae Hyoung Koo

IPC: H01L21/283

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/513 ,  H01L29/7881

Abstract: The present invention relates to a method of forming a dielectric layer of a flash memory device. In a process of forming a dielectric layer of a flash memory device, the dielectric layer may include a first oxide layer, a high dielectric layer, and a second oxide layer is formed. Accordingly, a leakage current characteristic and reliability of the flash memory device can be improved.

Abstract translation: 本发明涉及一种形成闪存器件的电介质层的方法。 在形成闪速存储器件的电介质层的过程中，介电层可以包括第一氧化物层，高电介质层和形成第二氧化物层。 因此，可以提高闪存器件的漏电流特性和可靠性。

公开(公告)号：US20080159919A1

公开(公告)日：2008-07-03

申请号：US11946770

申请日：2007-11-28

Applicant: June-Young LEE ,  Dong-Ho LEE

Inventor： June-Young LEE ,  Dong-Ho LEE

IPC: B01L11/00 ,  G01N33/566

CPC classification number: B01L3/508 ,  B01L1/52 ,  B01L2200/026 ,  B01L2300/045 ,  B01L2300/0636 ,  B01L2300/0809

Abstract: Provided is a biochip kit and a method capable of detecting the binding of target molecules in a biological sample to at least one probe on a biochip. The biochip kit includes a housing, a biochip, disposed in the housing, including at least one probe, and a lid, connectedly installed on the housing, such that the lid can open or close the housing.

Abstract translation: 提供了一种生物芯片试剂盒和能够检测生物样品中的靶分子与生物芯片上的至少一种探针的结合的方法。 生物芯片套件包括壳体，生物芯片，设置在壳体中，包括至少一个探针和连接安装在壳体上的盖，使得盖可以打开或关闭壳体。