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    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    5.
    发明公开
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230326882A1

    公开(公告)日：2023-10-12

    申请号：US17735099

    申请日：2022-05-02

    Applicant: United Microelectronics Corp.

    Inventor： Hui-Lung Chou ,  Ching-Li Yang ,  Chih-Sheng Chang ,  Chien-Ting Lin

    IPC: H01L23/00 ,  H01L23/58

    CPC classification number: H01L23/564 ,  H01L23/562 ,  H01L23/585

    Abstract: A semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, a seal ring structure including first and second interconnect structures, and a passivation layer on the seal ring structure and the second dielectric layer. The first interconnect structure is located in the first dielectric layer. The second interconnect structure is located in the second dielectric layer and connected to the first interconnect structure. The passivation layer has a spacer portion covering a sidewall of the second dielectric layer and a portion of the first dielectric layer. A ditch exists in the passivation layer and the first dielectric layer. The spacer portion is located between the ditch and the seal ring structure. The semiconductor structure is able to reduce time and power of an etching process for forming the ditch.

    INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF
    6.
    发明公开
    INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230215801A1

    公开(公告)日：2023-07-06

    申请号：US17670520

    申请日：2022-02-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/7684 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76877

    Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

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