公开(公告)号：US20250040233A1

公开(公告)日：2025-01-30

申请号：US18915263

申请日：2024-10-14

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng CHING ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

公开(公告)号：US20230268232A1

公开(公告)日：2023-08-24

申请号：US18142142

申请日：2023-05-02

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng CHING ,  Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU

IPC: H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823462 ,  H01L29/513 ,  H01L29/4908 ,  H01L27/0886 ,  H01L29/66795 ,  H01L21/823431 ,  H01L29/518 ,  H01L29/517

Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

公开(公告)号：US20170221765A1

公开(公告)日：2017-08-03

申请号：US15485270

申请日：2017-04-12

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng CHING ,  Guan-Lin CHEN

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFet, as compared to a FinFet including fins that do not include a dielectric disposed within a furrow.

公开(公告)号：US20210287945A1

公开(公告)日：2021-09-16

申请号：US17334848

申请日：2021-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Kuo-Cheng CHING ,  Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU

IPC: H01L21/8234 ,  H01L29/51 ,  H01L29/49 ,  H01L27/088 ,  H01L29/66

Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

公开(公告)号：US20190103322A1

公开(公告)日：2019-04-04

申请号：US16205419

申请日：2018-11-30

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng CHING ,  Carlos H. DIAZ ,  Jean-Pierre COLINGE

IPC: H01L21/8238 ,  H01L29/06 ,  B82Y40/00 ,  H01L29/786 ,  H01L29/16 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/775 ,  B82Y10/00

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

公开(公告)号：US20180233586A1

公开(公告)日：2018-08-16

申请号：US15953920

申请日：2018-04-16

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Chih-Hao WANG ,  Carlos H. DIAZ

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78696

Abstract: One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance.