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公开(公告)号：US20200091114A1
公开(公告)日：2020-03-19
申请号：US16133702
申请日：2018-09-18
发明人： Wei Kang Hsieh , Hung-Yi Kuo , Hao-Yi Tsai , Kuo Lung Pan , Tin-Hao Kuo , Yu-Chia Lai , Mao-Yen Chang , Po-Yuan Teng , Shu-Rong Chun
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
摘要： A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.
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公开(公告)号：US10461023B2
公开(公告)日：2019-10-29
申请号：US15884357
申请日：2018-01-30
发明人： Mao-Yen Chang , Hao-Yi Tsai , Kuo-Lung Pan , Tin-Hao Kuo , Tzung-Hui Lee , Teng-Yuan Lo , Hao-Chun Ting
IPC分类号： H01L23/498 , H01L23/31 , H01L21/48 , H01L25/10
摘要： Semiconductor package s and methods of forming the same are disclosed. The semiconductor package includes a chip, a redistribution circuit structure and a UBM pattern. The redistribution circuit structure is disposed over and electrically connected to the chip and includes a topmost conductive pattern. The UBM pattern is disposed over and electrically connected to the topmost conductive pattern, wherein the UBM pattern includes a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern.
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公开(公告)号：US20230387039A1
公开(公告)日：2023-11-30
申请号：US17881128
申请日：2022-08-04
发明人： Sung-Yueh Wu , Jen-Chun Liao , Mao-Yen Chang , Yu-Chia Lai , Chien Ling Hwang , Ching-Hua Hsieh
IPC分类号： H01L23/00 , H01L23/31 , H01L23/498 , H01L23/367 , H01L23/552 , H01L21/56 , H01L21/48
CPC分类号： H01L23/562 , H01L23/3107 , H01L23/49822 , H01L23/49838 , H01L23/367 , H01L23/552 , H01L21/56 , H01L21/4857
摘要： A semiconductor package includes a first package component comprising: an integrated circuit die; an encapsulant surrounding the integrated circuit die; and a fan-out structure electrically connected to the integrated circuit die, wherein a first opening extends completely through the fan-out structure and at least partially through the encapsulant in a cross-sectional view, and wherein the encapsulant at least completely surrounds the first opening in a top-down view. The semiconductor package further includes a package substrate bonded to the first package component.
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公开(公告)号：US20230178536A1
公开(公告)日：2023-06-08
申请号：US17655835
申请日：2022-03-22
发明人： Mao-Yen Chang , Yu-Chia Lai , Kuo-Lung Pan , Cheng-Shiuan Wong , Hsiu-Jen Lin , Ching-Hua Hsieh
IPC分类号： H01L25/00 , H01L25/065 , H01L23/00 , H01L21/56 , H01L21/683
CPC分类号： H01L25/50 , H01L25/0655 , H01L25/0652 , H01L24/19 , H01L24/20 , H01L21/568 , H01L21/6836 , H01L24/81 , H01L24/16 , H01L2224/2105 , H01L2224/16146 , H01L24/32 , H01L2224/32245 , H01L24/73 , H01L2224/73267 , H01L24/83
摘要： A method includes forming a reconstructed wafer, which includes placing a plurality of device dies over a carrier, encapsulating the plurality of device dies in an encapsulant, and forming a redistribution structure over the plurality of device dies and the encapsulant. The redistribution structure includes a plurality of dielectric layers and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes performing a trimming process on the reconstructed wafer. The trimming process forms a round edge for the reconstructed wafer. A sawing process is performed on the reconstructed wafer, so that the reconstructed wafer includes straight edges.
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公开(公告)号：US20220013422A1
公开(公告)日：2022-01-13
申请号：US16924208
申请日：2020-07-09
发明人： Mao-Yen Chang , Chih-Wei Lin , Hao-Yi Tsai , Kuo-Lung Pan , Chun-Cheng Lin , Tin-Hao Kuo , Yu-Chia Lai , Chih-Hsuan Tai
IPC分类号： H01L23/31 , H01L25/065 , H01L21/56 , H01L23/00 , H01L23/40 , H01L23/538 , H01L23/498 , H01L25/00
摘要： Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes.
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公开(公告)号：US11004827B2
公开(公告)日：2021-05-11
申请号：US16133702
申请日：2018-09-18
发明人： Wei Kang Hsieh , Hung-Yi Kuo , Hao-Yi Tsai , Kuo Lung Pan , Tin-Hao Kuo , Yu-Chia Lai , Mao-Yen Chang , Po-Yuan Teng , Shu-Rong Chun
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
摘要： A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.
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公开(公告)号：US20240113071A1
公开(公告)日：2024-04-04
申请号：US18150240
申请日：2023-01-05
发明人： Chung-Shi Liu , Mao-Yen Chang , Yu-Chia Lai , Kuo-Lung Pan , Hao-Yi Tsai , Ching-Hua Hsieh , Hsiu-Jen Lin , Po-Yuan Teng , Cheng-Chieh Wu , Jen-Chun Liao
CPC分类号： H01L24/95 , H01L21/563 , H01L23/3185 , H01L23/4012 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/83 , H01L25/18 , H10B80/00 , H01L2023/4081 , H01L2023/4087 , H01L2224/16227 , H01L2224/19 , H01L2224/211 , H01L2224/215 , H01L2224/32225 , H01L2224/73204 , H01L2224/83007 , H01L2224/83939 , H01L2224/95 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01074 , H01L2924/3512
摘要： An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.
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公开(公告)号：US11322421B2
公开(公告)日：2022-05-03
申请号：US16924208
申请日：2020-07-09
发明人： Mao-Yen Chang , Chih-Wei Lin , Hao-Yi Tsai , Kuo-Lung Pan , Chun-Cheng Lin , Tin-Hao Kuo , Yu-Chia Lai , Chih-Hsuan Tai
IPC分类号： H01L23/40 , H01L23/31 , H01L25/065 , H01L21/56 , H01L25/00 , H01L23/538 , H01L23/498 , H01L23/00
摘要： Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes.
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公开(公告)号：US20190131223A1
公开(公告)日：2019-05-02
申请号：US15884357
申请日：2018-01-30
发明人： Mao-Yen Chang , Hao-Yi Tsai , Kuo-Lung Pan , Tin-Hao Kuo , Tzung-Hui Lee , Teng-Yuan Lo , Hao-Chun Ting
IPC分类号： H01L23/498 , H01L23/31 , H01L21/48 , H01L25/10
摘要： Semiconductor package s and methods of forming the same are disclosed. The semiconductor package includes a chip, a redistribution circuit structure and a UBM pattern. The redistribution circuit structure is disposed over and electrically connected to the chip and includes a topmost conductive pattern. The UBM pattern is disposed over and electrically connected to the topmost conductive pattern, wherein the UBM pattern includes a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern.
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