公开(公告)号：US20190273147A1

公开(公告)日：2019-09-05

申请号：US15909838

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen CHENG ,  Cheng-Tung LIN ,  Chih-Wei CHANG ,  Hong-Mao LEE ,  Ming-Hsing TSAI ,  Sheng-Hsuan LIN ,  Wei-Jung LIN ,  Yan-Ming TSAI ,  Yu-Shiuan WANG ,  Hung-Hsu CHEN ,  Wei-Yip LOH ,  Ya-Yi CHENG

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/326 ,  H01L29/78

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

公开(公告)号：US20190273023A1

公开(公告)日：2019-09-05

申请号：US15909762

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yip LOH ,  Chih-Wei CHANG ,  Hong-Mao LEE ,  Chun-Hsien HUANG ,  Yu-Ming HUANG ,  Yan-Ming TSAI ,  Yu-Shiuan WANG ,  Hung-Hsu CHEN ,  Yu-Kai CHEN ,  Yu-Wen CHENG

IPC: H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L23/522

Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.

公开(公告)号：US20230411242A1

公开(公告)日：2023-12-21

申请号：US17807476

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kan-Ju LIN ,  Lin-Yu HUANG ,  Min-Hsuan LU ,  Wei-Yip LOH ,  Hong-Mao LEE ,  Harry CHIEN

IPC: H01L23/48 ,  H01L29/417 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L23/481 ,  H01L29/41733 ,  H01L21/76898 ,  H01L29/401 ,  H01L29/45

Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.