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公开(公告)号：US11631810B2
公开(公告)日：2023-04-18
申请号：US17233755
申请日：2021-04-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chao-Yang Chen , Chun-Yang Tsai , Kuo-Ching Huang , Wen-Ting Chu , Pili Huang , Cheng-Jun Wu
IPC: H01L27/088 , H01L21/8236 , H01L45/00 , H01L27/24
Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnects arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnects. The bottom electrode includes a first material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. The bottom electrode is between the data storage layer and the substrate. A reactivity reducing layer includes a second material and has a second electronegativity that is greater than or equal to the first electronegativity. The second material contacts a lower surface of the bottom electrode that faces the substrate.
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公开(公告)号：US20210043257A1
公开(公告)日：2021-02-11
申请号：US17082232
申请日：2020-10-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chao-Yang Chen , Cheng-Jun Wu , Chun-Yang Tsai , Kuo-Ching Huang
IPC: G11C13/00
Abstract: In some embodiments, the present disclosure relates to a method, comprising the performing of a reset operation to a resistive random access memory (RRAM) cell. A first voltage bias having a first polarity is applied to the RRAM cell. An absolute value of the first voltage bias is greater than an absolute value of a first reset voltage. The application of the first voltage bias induces the RRAM cell to change from a low resistance to an intermediate resistance greater than the low resistance. A second voltage bias having a second polarity oppose to the first polarity is then applied to the RRAM cell. An absolute value of the second reset voltage is less than an absolute value of the second voltage bias and less than the absolute value of the first reset voltage. The application of the second voltage bias induces the RRAM cell to have a high resistance.
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公开(公告)号：US11107528B2
公开(公告)日：2021-08-31
申请号：US17082232
申请日：2020-10-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chao-Yang Chen , Cheng-Jun Wu , Chun-Yang Tsai , Kuo-Ching Huang
Abstract: In some embodiments, the present disclosure relates to a method, comprising the performing of a reset operation to a resistive random access memory (RRAM) cell. A first voltage bias having a first polarity is applied to the RRAM cell. An absolute value of the first voltage bias is greater than an absolute value of a first reset voltage. The application of the first voltage bias induces the RRAM cell to change from a low resistance to an intermediate resistance greater than the low resistance. A second voltage bias having a second polarity oppose to the first polarity is then applied to the RRAM cell. An absolute value of the second reset voltage is less than an absolute value of the second voltage bias and less than the absolute value of the first reset voltage. The application of the second voltage bias induces the RRAM cell to have a high resistance.
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公开(公告)号：US20210242400A1
公开(公告)日：2021-08-05
申请号：US17233755
申请日：2021-04-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chao-Yang Chen , Chun-Yang Tsai , Kuo-Ching Huang , Wen-Ting Chu , Pili Huang , Cheng-Jun Wu
Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnects arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnects. The bottom electrode includes a first material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. The bottom electrode is between the data storage layer and the substrate. A reactivity reducing layer includes a second material and has a second electronegativity that is greater than or equal to the first electronegativity. The second material contacts a lower surface of the bottom electrode that faces the substrate.
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公开(公告)号：US20210098630A1
公开(公告)日：2021-04-01
申请号：US17117711
申请日：2020-12-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mickey Hsieh , Chun-Yang Tsai , Kuo-Ching Huang , Kuo-Chi Tu , Pili Huang , Cheng-Jun Wu , Chao-Yang Chen
IPC: H01L29/78 , H01L27/11507 , H01L49/02 , H01L29/66 , H01L29/51 , H01L27/1159 , H01L21/28
Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.
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Patent Agency Ranking
公开(公告)号：US11594632B2
公开(公告)日：2023-02-28
申请号：US17117711
申请日：2020-12-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mickey Hsieh , Chun-Yang Tsai , Kuo-Ching Huang , Kuo-Chi Tu , Pili Huang , Cheng-Jun Wu , Chao-Yang Chen
IPC: H01L29/78 , H01L27/11507 , H01L49/02 , H01L29/66 , H01L29/51 , H01L27/1159 , H01L21/28
Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.
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公开(公告)号：US10985316B2
公开(公告)日：2021-04-20
申请号：US16359092
申请日：2019-03-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chao-Yang Chen , Chun-Yang Tsai , Kuo-Ching Huang , Wen-Ting Chu , Pili Huang , Cheng-Jun Wu
IPC: H01L27/088 , H01L21/8236 , H01L45/00 , H01L27/24
Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnect layers arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnect layers. A lower surface of the bottom electrode includes a material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. A reactivity reducing layer contacts the lower surface of the bottom electrode. The reactivity reducing layer has a second electronegativity that is greater than or equal to the first electronegativity.
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公开(公告)号：US11696521B2
公开(公告)日：2023-07-04
申请号：US16939497
申请日：2020-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chao-Yang Chen , Chun-Yang Tsai , Kuo-Ching Huang , Wen-Ting Chu , Cheng-Jun Wu
CPC classification number: H10N70/883 , G11C13/0007 , H10B63/00 , H10N70/021 , H10N70/841
Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.
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公开(公告)号：US20220254791A1
公开(公告)日：2022-08-11
申请号：US17168317
申请日：2021-02-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Cheng-Jun Wu , Yu-Wei Jiang , Sheng-Chih Lai
IPC: H01L27/1157 , H01L23/522 , H01L27/11524 , H01L27/11556 , H01L27/11582
Abstract: The present disclosure relates to an integrated chip including a three-dimensional memory array. The three-dimensional memory array includes a first local line and a second local line that are elongated vertically, a first memory cell extending between the first local line and the second local line, and a second memory cell directly under the first memory cell, extending between the first local line and the second local line, and coupled in parallel with the first memory cell. The first memory cell is coupled to a first word line and the second memory cell is coupled to a second word line. The first word line and the second word line are elongated horizontally. A first global line is disposed at a first height and is elongated horizontally. A first selector extends vertically from the first local line to the first global line.
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公开(公告)号：US20210135105A1
公开(公告)日：2021-05-06
申请号：US16939497
申请日：2020-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chao-Yang Chen , Chun-Yang Tsai , Kuo-Ching Huang , Wen-Ting Chu , Cheng-Jun Wu
Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.
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