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1.发明授权Weak erase after programming to improve data retention in charge-trapping memory 有权程序设计后擦除弱，以提高电荷俘获存储器中的数据保留公开(公告)号：US09324439B1
公开(公告)日：2016-04-26
申请号：US14518340
申请日：2014-10-20
发明人： Hong-Yan Chen , Yingda Dong , Ching-Huang Lu
CPC分类号： G11C16/14 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/3404 , G11C16/3409 , G11C16/3413
摘要： Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.
摘要翻译： 提供技术来改善电荷俘获存储器件中的长期数据保持。 除了存储大多数电荷的主电荷捕获层之外，存储器件可以包括隧道层，其包括工程化隧道势垒，例如氧化物 - 氮化物 - 氧化物。 在编程之后，隧道层中的氮化物也可能存储一些电荷。 在编程之后，除了将空穴注入到形成中性电子 - 空穴偶极子的隧道层中以代替电子之外，还执行了从隧道层去除一些电子的数据保留操作。 这些机制倾向于降低阈值电压。 此外，数据保持操作将电荷和空穴重新分布在电荷俘获层内部，导致阈值电压的增加，这在数据保持操作优化时大致抵消了减少。
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2.发明申请Method Of Reducing Hot Electron Injection Type Of Read Disturb In Dummy Memory Cells 有权减少热电子注射类型在虚拟记忆体中读取干扰的方法公开(公告)号：US20160217865A1
公开(公告)日：2016-07-28
申请号：US14924379
申请日：2015-10-27
发明人： Hong-Yan Chen , Yingda Dong , Wei Zhao
CPC分类号： G11C16/28 , G11C7/1051 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3427
摘要： Read disturb is reduced for dummy memory cells in a charge-trapping memory device such as a 3D memory device. The memory device includes a selected NAND string and an unselected NAND string. In the unselected NAND string, a dummy memory cell is adjacent to a select gate transistor. During a read operation involving the selected NAND string, a voltage of the dummy memory cell is increased in two steps to minimize a gradient in a channel of the unselected NAND string between the dummy memory cell and the select gate transistor. During the first step, the select gate transistor is conductive so that the channel is connected to a driven bit line. During the second step, the select gate transistor is non-conductive. Voltages on unselected word lines can also be increased in two steps to set a desired channel boosting level in the unselected NAND string.
摘要翻译： 对于诸如3D存储器装置的电荷俘获存储器件中的虚拟存储器单元，读取干扰被减少。 存储器件包括所选择的NAND串和未选择的NAND串。 在未选择的NAND串中，虚拟存储单元与选择栅极晶体管相邻。 在涉及所选择的NAND串的读取操作期间，两个步骤增加了虚拟存储单元的电压，以最小化虚拟存储单元和选择栅极晶体管之间未被选择的NAND串的通道中的梯度。 在第一步骤期间，选择栅极晶体管导通，使得沟道连接到从动位线。 在第二步骤期间，选择栅极晶体管是非导通的。 未选择字线上的电压也可以分两步增加，以在未选择的NAND串中设置所需的通道升压电平。
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3.发明授权公开(公告)号：US09349478B2
公开(公告)日：2016-05-24
申请号：US14500660
申请日：2014-09-29
发明人： Jiahui Yuan , Yingda Dong , Charles Kwong , Hong-Yan Chen , Liang Pang
CPC分类号： G11C16/3427 , G06F11/1068 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3459 , G11C29/52
摘要： A read operation compensates for program disturb when distinguishing between an erased-state and a lowest programmed data state, where the program disturb is a function of the data state of an adjacent, previously-programmed memory cell on a common charge-trapping layer. A programming operation avoids program disturb of the programmed data states by using asymmetric pass voltages. Before reading the memory cells on a selected word line (WLn), the memory cells on the adjacent, previously-programmed word line (WLn−1) are read. The read operation for WLn uses multiple read voltages—one for each data state on WLn−1, and one of the read results is selected based on the data state of the adjacent memory cell. Other read operations distinguish between each pair of adjacent programmed data states using a read voltage which is independent of the data state of the adjacent memory cell.
摘要翻译： 当识别擦除状态和最低编程数据状态时，读取操作补偿程序干扰，其中程序干扰是公共电荷俘获层上相邻的预先编程的存储器单元的数据状态的函数。 编程操作通过使用不对称通过电压来避免编程数据状态的程序干扰。 在读取所选字线（WLn）上的存储单元之前，读取相邻的预先编程的字线（WLn-1）上的存储单元。 WLn的读取操作使用多个读取电压 - 一个用于WLn-1上的每个数据状态，并且基于相邻存储器单元的数据状态选择一个读取结果。 其他读取操作使用独立于相邻存储器单元的数据状态的读取电压来区分每对相邻的编程数据状态。
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公开(公告)号：US09286994B1
公开(公告)日：2016-03-15
申请号：US14669247
申请日：2015-03-26
发明人： Hong-Yan Chen , Yingda Dong , Wei Zhao
CPC分类号： G11C16/28 , G11C7/1051 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3427
摘要： Read disturb is reduced for dummy memory cells in a charge-trapping memory device such as a 3D memory device. The memory device includes a selected NAND string and an unselected NAND string. In the unselected NAND string, a dummy memory cell is adjacent to a select gate transistor. During a read operation involving the selected NAND string, a voltage of the dummy memory cell is increased in two steps to minimize a gradient in a channel of the unselected NAND string between the dummy memory cell and the select gate transistor. During the first step, the select gate transistor is conductive so that the channel is connected to a driven bit line. During the second step, the select gate transistor is non-conductive. Voltages on unselected word lines can also be increased in two steps to set a desired channel boosting level in the unselected NAND string.
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5.发明授权Method of reducing hot electron injection type of read disturb in dummy memory cells 有权在虚拟存储器单元中减少热电子注入类型的读取干扰的方法公开(公告)号：US09406391B1
公开(公告)日：2016-08-02
申请号：US14924379
申请日：2015-10-27
发明人： Hong-Yan Chen , Yingda Dong , Wei Zhao
CPC分类号： G11C16/28 , G11C7/1051 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3427
摘要： Read disturb is reduced for dummy memory cells in a charge-trapping memory device such as a 3D memory device. The memory device includes a selected NAND string and an unselected NAND string. In the unselected NAND string, a dummy memory cell is adjacent to a select gate transistor. During a read operation involving the selected NAND string, a voltage of the dummy memory cell is increased in two steps to minimize a gradient in a channel of the unselected NAND string between the dummy memory cell and the select gate transistor. During the first step, the select gate transistor is conductive so that the channel is connected to a driven bit line. During the second step, the select gate transistor is non-conductive. Voltages on unselected word lines can also be increased in two steps to set a desired channel boosting level in the unselected NAND string.
摘要翻译： 对于诸如3D存储器装置的电荷俘获存储器件中的虚拟存储器单元，读取干扰被减少。 存储器件包括所选择的NAND串和未选择的NAND串。 在未选择的NAND串中，虚拟存储单元与选择栅极晶体管相邻。 在涉及所选择的NAND串的读取操作期间，两个步骤增加了虚拟存储单元的电压，以最小化虚拟存储单元和选择栅极晶体管之间未被选择的NAND串的通道中的梯度。 在第一步骤期间，选择栅极晶体管导通，使得沟道连接到从动位线。 在第二步骤期间，选择栅极晶体管是非导通的。 未选择字线上的电压也可以分两步增加，以在未选择的NAND串中设置所需的通道升压电平。
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6.发明授权Reducing hot electron injection type of read disturb in 3D non-volatile memory 有权在3D非易失性存储器中减少热电子注入类型的读取干扰公开(公告)号：US09336892B1
公开(公告)日：2016-05-10
申请号：US14728615
申请日：2015-06-02
发明人： Hong-Yan Chen , Yingda Dong , Charles Kwong
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3459 , G11C2211/5621
摘要： Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages at the end of a sensing operation. In an example read operation, the magnitude of a selected word line voltage is increased to be equal to pass voltages of unselected word lines, and the selected and unselected word line are ramped down at the same time, to avoid creating a channel gradient. In an example verify operation, the above procedure can be followed when the selected word line is at a source-side or middle range among all word lines. When the selected word line is at a drain-side among all word lines, a source-side select gate can be ramped down before the selected word line and a drain-side select gate can be ramped down after the selected word line.
摘要翻译： 通过控制字线的幅度和时序并在感测操作结束时选择栅极斜坡下降电压，在3D存储器件中减少了由于热电子注入引起的读取干扰。 在示例性读取操作中，所选择的字线电压的大小增加到等于未选择字线的通过电压，并且所选择的和未选择的字线同时斜降，以避免产生通道梯度。 在示例验证操作中，当所选字线在所有字线之间的源侧或中间范围时，可以遵循上述过程。 当所选择的字线位于所有字线之间的漏极侧时，在选择的字线之前可以使源极选择栅极向下斜坡，并且在选择的字线之后，可以将漏极侧选择栅极向下斜坡。
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7.发明申请Weak Erase After Programming To Improve Data Retention In Charge-Trapping Memory 有权编程后弱化擦除电荷捕获存储器中的数据保留公开(公告)号：US20160111164A1
公开(公告)日：2016-04-21
申请号：US14518340
申请日：2014-10-20
发明人： Hong-Yan Chen , Yingda Dong , Ching-Huang Lu
CPC分类号： G11C16/14 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/3404 , G11C16/3409 , G11C16/3413
摘要： Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.
摘要翻译： 提供技术来改善电荷俘获存储器件中的长期数据保持。 除了存储大多数电荷的主电荷捕获层之外，存储器件可以包括隧道层，其包括工程化隧道势垒，例如氧化物 - 氮化物 - 氧化物。 在编程之后，隧道层中的氮化物也可能存储一些电荷。 在编程之后，除了将空穴注入到形成中性电子 - 空穴偶极子的隧道层中以代替电子之外，还执行了从隧道层去除一些电子的数据保留操作。 这些机制倾向于降低阈值电压。 此外，数据保持操作将电荷和空穴重新分布在电荷俘获层内部，导致阈值电压的增加，这在数据保持操作优化时大致抵消了减少。
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8.发明申请Controlling Pass Voltages To Minimize Program Disturb In Charge-Trapping Memory 有权控制通过电压以最大限度地减少电荷陷阱存储器中的程序干扰公开(公告)号：US20160071595A1
公开(公告)日：2016-03-10
申请号：US14481304
申请日：2014-09-09
发明人： Yingda Dong , Hong-Yan Chen
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0466 , G11C16/0483 , G11C16/3427 , G11C16/3459
摘要： Techniques are provided for preventing program disturb of unselected memory cells during programming of a selected memory cell in a NAND string which includes a continuous charge-trapping layer, either in a two-dimensional or three-dimensional configuration. In such a NAND string, regions between the memory cells can be inadvertently programmed as parasitic cells due to the program voltage and pass voltages on the word lines. For programmed cells, an upshift in threshold voltage due to a parasitic cell can be avoided by providing a higher pass voltage on an adjacent later-programmed word line than on an adjacent previously-programmed word line. For erased cells, an upshift in threshold voltage due to the parasitic cells can be reduced by progressively lowering the pass voltage on the adjacent later-programmed word line. The lowering can occur when memory cells of a lowest target data state complete programming.
摘要翻译： 提供技术用于防止在包括二维或三维配置的连续电荷俘获层的NAND串中的所选存储单元的编程期间防止未选择存储单元的程序干扰。 在这种NAND串中，由于程序电压和字线上的通过电压，存储单元之间的区域可能被无意地编程为寄生单元。 对于编程单元，通过在相邻的后面编程的字线上提供比在相邻的预先编程的字线上更高的通过电压，可以避免由寄生电池引起的阈值电压升档。 对于已擦除的单元，可以通过逐渐降低相邻的后编程字线上的通过电压来降低由寄生电池引起的阈值电压升档。 当最低目标数据状态的存储单元完成编程时，可能会发生降低。
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9.发明申请Read With Look-Back Combined With Programming With Asymmetric Boosting In Memory 有权阅读与回想结合编程与不对称提升在内存公开(公告)号：US20160093390A1
公开(公告)日：2016-03-31
申请号：US14500660
申请日：2014-09-29
发明人： Jiahui Yuan , Yingda Dong , Charles Kwong , Hong-Yan Chen , Liang Pang
CPC分类号： G11C16/3427 , G06F11/1068 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3459 , G11C29/52
摘要： A read operation compensates for program disturb when distinguishing between an erased-state and a lowest programmed data state, where the program disturb is a function of the data state of an adjacent, previously-programmed memory cell on a common charge-trapping layer. The read operation occurs in connection with a programming operation which avoids program disturb of the programmed data states by using asymmetric pass voltages. Before reading the memory cells on a selected word line (WLn), the memory cells on the adjacent, previously-programmed word line (WLn−1) are read. The read operation for WLn uses multiple read voltages—one for each data state on WLn−1, and one of the read results is selected based on the data state of the adjacent memory cell. Other read operations distinguish between each pair of adjacent programmed data states using a read voltage which is independent of the data state of the adjacent memory cell.
摘要翻译： 当识别擦除状态和最低编程数据状态时，读取操作补偿程序干扰，其中程序干扰是公共电荷俘获层上相邻的预先编程的存储器单元的数据状态的函数。 读操作与编程操作相关，通过使用不对称通过电压避免编程数据状态的程序干扰。 在读取所选字线（WLn）上的存储单元之前，读取相邻的预先编程的字线（WLn-1）上的存储单元。 WLn的读取操作使用多个读取电压 - 一个用于WLn-1上的每个数据状态，并且基于相邻存储器单元的数据状态选择一个读取结果。 其他读取操作使用独立于相邻存储器单元的数据状态的读取电压来区分每对相邻的编程数据状态。
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10.发明申请EFFICIENT REPROGRAMMING METHOD FOR TIGHTENING A THRESHOLD VOLTAGE DISTRIBUTION IN A MEMORY DEVICE 有权用于在存储器件中加强阈值电压分配的有效的重现方法公开(公告)号：US20150325297A1
公开(公告)日：2015-11-12
申请号：US14272758
申请日：2014-05-08
发明人： Liang Pang , Hong-Yan Chen , Yingda Dong
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0466 , G11C16/0483 , G11C16/3418 , G11C16/3459
摘要： Techniques are provided for programming memory cells while reducing the effects of detrapping which cause a downshift in the threshold voltage distribution. Detrapping is particularly problematic for charge-trapping memory cells such as in a 3D stacked non-volatile memory device. During programming, a temporary lockout mode is provided for memory cells which pass a verify test. During a checkpoint program-verify iteration, all memory cells of a target data state are subject to the verify test. The memory cells in the temporary lockout mode are therefore subject to the verify test a second time. Memory cells that fail the verify test in the checkpoint program-verify iteration are programmed further. A normal or slow programming mode is used for a memory cell depending on whether it had reached the temporary lockout mode. Threshold voltage distributions are narrowed by reprogramming some of the memory cells.
摘要翻译： 提供了用于编程存储器单元的技术，同时减少了导致阈值电压分布中的降档的去夹带的影响。 解扣对于诸如在3D堆叠的非易失性存储器件中的电荷捕获存储器单元是特别有问题的。 在编程期间，为通过验证测试的存储器单元提供临时锁定模式。 在检查点程序验证迭代期间，目标数据状态的所有存储单元都进行验证测试。 因此，临时锁定模式中的存储单元第二次进行验证测试。 在检查点程序验证迭代中验证测试失败的内存单元进一步编程。 根据存储单元是否达到临时锁定模式，正常或慢速编程模式被用于存储单元。 通过重新编程某些存储器单元，阈值电压分布变窄。
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