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    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20130341595A1

    公开(公告)日：2013-12-26

    申请号：US13789873

    申请日：2013-03-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-moon LEE ,  Young-jin CHO

    IPC: H01L29/15

    CPC classification number: H01L29/78 ,  H01L29/0657 ,  H01L29/1075 ,  H01L29/1079 ,  H01L29/15 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/7783

    Abstract: Semiconductor devices including a substrate (e.g., silicon substrate), a multi-layer structure disposed on a portion of the substrate, and at least one electrode disposed on the multi-layer structure and methods of manufacturing the same are provided. The multi-layer structure may include an active layer containing a Group III-V material and a current blocking layer disposed between the substrate and the active layer. The semiconductor device may further include a buffer layer disposed between the substrate and the active layer. In a case that the substrate is a p-type, the buffer layer may be an n-type material layer and the current blocking layer may be a p-type material layer. The current blocking layer may contain a Group III-V material. A mask layer having an opening may be disposed on the substrate so that the multi-layer structure may be disposed on the portion of the substrate exposed by the opening.

    MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    2.
    发明申请
    MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20200042247A1

    公开(公告)日：2020-02-06

    申请号：US16445340

    申请日：2019-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sueng-chul RYU ,  Young-jin CHO

    IPC: G06F3/06

    Abstract: A memory device includes at least one memory configured to communicate with a memory controller; and a memory accelerator provided separate from the at least one memory and configured to communicate with the at least one memory, wherein the memory accelerator includes a compatible logic configured to perform a data processing/restoration operation adaptively corresponding to a data processing/restoration type of the memory controller.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150041764A1

    公开(公告)日：2015-02-12

    申请号：US14521910

    申请日：2014-10-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-moon LEE ,  Young-jin CHO

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/205 ,  H01L29/15

    CPC classification number: H01L29/78 ,  H01L29/0657 ,  H01L29/1075 ,  H01L29/1079 ,  H01L29/15 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/7783

    Abstract: Semiconductor devices including a substrate (e.g., silicon substrate), a multi-layer structure disposed on a portion of the substrate, and at least one electrode disposed on the multi-layer structure and methods of manufacturing the same are provided. The multi-layer structure may include an active layer containing a Group III-V material and a current blocking layer disposed between the substrate and the active layer. The semiconductor device may further include a buffer layer disposed between the substrate and the active layer. In a case that the substrate is a p-type, the buffer layer may be an n-type material layer and the current blocking layer may be a p-type material layer. The current blocking layer may contain a Group III-V material. A mask layer having an opening may be disposed on the substrate so that the multi-layer structure may be disposed on the portion of the substrate exposed by the opening.

    Abstract translation: 提供了包括衬底（例如，硅衬底），设置在衬底的一部分上的多层结构以及设置在多层结构上的至少一个电极的半导体器件及其制造方法。 多层结构可以包括含有III-V族材料的有源层和设置在衬底和有源层之间的电流阻挡层。 半导体器件还可以包括设置在衬底和有源层之间的缓冲层。 在基板是p型的情况下，缓冲层可以是n型材料层，电流阻挡层可以是p型材料层。 电流阻挡层可以含有III-V族材料。 具有开口的掩模层可以设置在基板上，使得多层结构可以设置在由开口暴露的基板的部分上。

    MEMORY CONTROLLER DETERMINING ENDURANCE DEGRADATION, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE MEMORY CONTROLLER
    7.
    发明申请
    MEMORY CONTROLLER DETERMINING ENDURANCE DEGRADATION, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE MEMORY CONTROLLER 审中-公开

    公开(公告)号：US20200159619A1

    公开(公告)日：2020-05-21

    申请号：US16415906

    申请日：2019-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eun Chu OH ,  Jeong-ho LEE ,  Young-jin CHO

    IPC: G06F11/10 ,  G11C13/00 ,  G11C29/52

    Abstract: Provided are a memory controller determining degradation in endurance, a memory system including the memory controller, and a method of operating the memory controller. The memory controller includes: an error correction code (ECC) circuit configured to detect an error from data read from a memory device; and an endurance determination circuit configured to check a first counting value indicating a number of writing operations on the memory device and a second counting value indicating, based on the data read from the memory device, at least one of: a number of first memory cells of the memory device, each of the first memory cells having an error and a number of second memory cells of the memory device in a certain logic state, and configured to perform a first determination operation for determining whether endurance of the memory device has degraded based on a checking result.

    SUBSTRATE STRUCTURES AND SEMICONDUCTOR DEVICES EMPLOYING THE SAME
    8.
    发明申请
    SUBSTRATE STRUCTURES AND SEMICONDUCTOR DEVICES EMPLOYING THE SAME 审中-公开
    使用其的基板结构和半导体器件

    公开(公告)号：US20140299885A1

    公开(公告)日：2014-10-09

    申请号：US14070964

    申请日：2013-11-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-moon LEE ,  Young-jin CHO ,  Myong-Jae LEE

    IPC: H01L29/20

    CPC classification number: H01L29/20 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02546

    Abstract: A substrate structure includes a substrate, a nucleation layer on the substrate and including a group III-V compound semiconductor material having a lattice constant that is different from that of the substrate by less than 1%, and a buffer layer on the nucleation layer and including first and second layers, wherein the first and second layers include group III-V compound semiconductor materials having lattice constants that are greater than that of the nucleation layer by 4% or more.

    Abstract translation: 衬底结构包括衬底，在衬底上的成核层，并且包括具有不同于衬底的晶格常数小于1％的晶格常数的III-V族化合物半导体材料，以及成核层上的缓冲层和 包括第一层和第二层，其中第一层和第二层包括具有大于成核层的晶格常数4％或更多的晶格常数的III-V族化合物半导体材料。

    LIGHT-EMITTING DIODE (LED) PACKAGE HAVING FLIP-CHIP BONDING STRUCTURE
    9.
    发明申请
    LIGHT-EMITTING DIODE (LED) PACKAGE HAVING FLIP-CHIP BONDING STRUCTURE 有权
    发光二极管（LED）包装有片状贴片结构

    公开(公告)号：US20140252402A1

    公开(公告)日：2014-09-11

    申请号：US14197889

    申请日：2014-03-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kun-jeong LEE ,  Young-jin CHO

    IPC: H01L33/62

    CPC classification number: H01L33/62 ,  H01L33/486 ,  H01L2224/13 ,  H01L2224/16245

    Abstract: A light-emitting diode (LED) package includes a package substrate, a first electrode pad, a second electrode pad, an upper insulating layer and an LED chip. The first electrode pad is disposed on an upper surface of the package substrate and includes a groove. The second electrode pad includes a protruding portion disposed in the groove of the first electrode pad. The upper insulating layer insulates the first electrode pad from the second electrode pad on the package substrate. The LED chip includes a first electrode and a second electrode which are respectively electrically connected in the form of a flip-chip to the first electrode pad and the protruding portion of the second electrode pad.

    Abstract translation: 发光二极管（LED）封装包括封装衬底，第一电极焊盘，第二电极焊盘，上绝缘层和LED芯片。 第一电极焊盘设置在封装基板的上表面上并且包括凹槽。 第二电极焊盘包括设置在第一电极焊盘的凹槽中的突出部分。 上绝缘层将第一电极焊盘与第二电极焊盘绝缘在封装衬底上。 LED芯片包括分别以倒装芯片的形式电连接到第一电极焊盘和第二电极焊盘的突出部分的第一电极和第二电极。

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