公开(公告)号：US20150055401A1

公开(公告)日：2015-02-26

申请号：US14537387

申请日：2014-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung KIM ,  Yongchul OH ,  Dongsoo WOO ,  Hyun-Woo CHUNG ,  Gyoyoung JIN ,  Sungkwan CHOI ,  Hyeongsun HONG ,  Yoosang HWANG

IPC: G11C11/4096 ,  G11C11/404 ,  H01L29/66 ,  H01L27/108 ,  H01L29/423

CPC classification number: G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

Abstract translation: 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。

公开(公告)号：US20150001617A1

公开(公告)日：2015-01-01

申请号：US14488426

申请日：2014-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik KIM ,  HyeongSun HONG ,  Yongchul OH ,  Yoosang HWANG

IPC: H01L27/105 ,  H01L23/538 ,  H01L29/51 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L27/1052 ,  H01L23/5386 ,  H01L27/088 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/515 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided.

Abstract translation: 制造半导体器件的方法可以包括在衬底中形成第一沟槽以限定鳍片图案并形成填充第一沟槽的较低区域的埋入电介质图案。 第一个沟槽并行延伸。 栅电介质层形成在第一沟槽的上内侧壁上，并且在包括栅极电介质层的衬底上形成填充第一沟槽的栅极导电层。 栅极导电层，栅极电介质层和鳍状图案被图案化以形成与第一沟槽交叉并限定有源支柱的第二沟槽。 还可以提供半导体器件。