公开(公告)号：US20240222284A1

公开(公告)日：2024-07-04

申请号：US18228278

申请日：2023-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongju Cho ,  Jingu Kim ,  Yieok Kwon ,  Wooyoung Kim ,  Gongje Lee ,  Sangkyu Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/10

CPC classification number: H01L23/5386 ,  H01L23/10 ,  H01L24/05 ,  H01L24/13 ,  H01L24/46 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/05024 ,  H01L2224/13008 ,  H01L2224/46

Abstract: Semiconductor package includes lower redistribution layer providing first redistribution wirings and having first region and second region surrounding the first region, semiconductor chip disposed on the first region and electrically connected to the first redistribution wirings, sealing member covering the semiconductor chip on the lower redistribution layer, plurality of vertical conductive structures penetrating the sealing member on the second region and electrically connected to the first redistribution wirings, upper redistribution layer disposed on the sealing member and having second redistribution wirings electrically connected to the plurality of vertical conductive structures and plurality of bonding pads. The vertical conductive structures are bonded to the bonding pad and extend vertically from the plurality of bonding pads. The vertical conductive structure includes first to third conductive pillar portions sequentially stacked. The first conductive pillar portion has first length and the third conductive pillar portion has third length greater than the first length.

公开(公告)号：US20230178492A1

公开(公告)日：2023-06-08

申请号：US18161066

申请日：2023-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5386 ,  H01L25/0657 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/73 ,  H01L23/3128 ,  H01L24/08 ,  H01L23/5385 ,  H01L2224/08235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2224/73204

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

公开(公告)号：US11569175B2

公开(公告)日：2023-01-31

申请号：US17239141

申请日：2021-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

公开(公告)号：US20220068822A1

公开(公告)日：2022-03-03

申请号：US17239141

申请日：2021-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

公开(公告)号：US12119305B2

公开(公告)日：2024-10-15

申请号：US18161066

申请日：2023-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L24/08 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/08235 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/0652

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

公开(公告)号：US20240006342A1

公开(公告)日：2024-01-04

申请号：US18119327

申请日：2023-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingu Kim ,  Yieok Kwon ,  Sangkyu Lee ,  Taesung Jeong

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/29

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49811 ,  H01L23/49894 ,  H01L23/295 ,  H01L24/16 ,  H01L2224/16227 ,  H10B80/00

Abstract: A semiconductor package includes a first redistribution structure including a first redistribution layer; a semiconductor chip on a first surface of the first redistribution structure and including a connection pad electrically connected to the first redistribution layer; an encapsulant that surrounds at least a portion of the semiconductor chip; a second redistribution structure on the encapsulant and including a second redistribution layer; a through-via structure that extends through the encapsulant and electrically connects the first redistribution layer to the second redistribution layer; an organic material layer between the through-via structure and the encapsulant and having an elongation rate greater than an elongation rate of the encapsulant; and a bump structure on a second surface of the first redistribution structure.

公开(公告)号：US10930525B2

公开(公告)日：2021-02-23

申请号：US16665745

申请日：2019-10-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yieok Kwon ,  Ikjun Choi

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498

Abstract: A carrier substrate includes a core layer and at least one unit pattern portion, and the unit pattern portion includes a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, a second metal layer disposed on the release layer, and a third metal layer disposed on the second metal layer and covering side surfaces of the release layer, and a method of manufacturing a semiconductor package using the carrier substrate.