公开(公告)号：US20170207130A1

公开(公告)日：2017-07-20

申请号：US15386843

申请日：2016-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Jung PARK ,  Ju-Hyun KIM ,  Hoyoung KIM ,  Boun YOON ,  TaeYong KWON ,  Sangkyun KIM ,  Sanghyun PARK

IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/092 ,  H01L21/3105

CPC classification number: H01L21/823807 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/092

Abstract: A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and expose a portion of the lower buffer layer, forming a second channel semiconductor layer to fill the opening and include a first portion protruding above the capping insulating layer, performing a first CMP process to remove at least a portion of the first portion, removing the capping insulating layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding above the first channel semiconductor layer.

公开(公告)号：US20170194330A1

公开(公告)日：2017-07-06

申请号：US15255652

申请日：2016-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghun LEE ,  TaeYong KWON ,  Dongwon KIM

IPC: H01L27/11 ,  H01L29/417 ,  H01L27/092

Abstract: An SRAM device includes first, second and third transistors, which are used as a pass gate transistor, a pull-down transistor, and a pull-up transistor, respectively. A channel region of each transistor may include a plurality of semiconductor sheets that are vertically stacked on a substrate. The semiconductor sheets used as the channel regions of the first and second transistors may have a width greater than the semiconductor sheets used as channel regions of the third transistor.

公开(公告)号：US20200098918A1

公开(公告)日：2020-03-26

申请号：US16693439

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jong LEE ,  Sanghyuk HONG ,  TaeYong KWON ,  Sunjung KIM ,  Cheol KIM

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L21/8238

Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.

公开(公告)号：US20200185393A1

公开(公告)日：2020-06-11

申请号：US16793912

申请日：2020-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun LEE ,  TaeYong KWON ,  Dongwon KIM

IPC: H01L27/11 ,  H01L29/417 ,  H01L27/092 ,  H01L27/11582

Abstract: An SRAM device includes first, second and third transistors, which are used as a pass gate transistor, a pull-down transistor, and a pull-up transistor, respectively. A channel region of each transistor may include a plurality of semiconductor sheets that are vertically stacked on a substrate. The semiconductor sheets used as the channel regions of the first and second transistors may have a width greater than the semiconductor sheets used as channel regions of the third transistor.

公开(公告)号：US20170345679A1

公开(公告)日：2017-11-30

申请号：US15602599

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeYong KWON ,  Sangjin KIM ,  Donghoon HWANG ,  Sebeom OH ,  Yunkyeong JANG

IPC: H01L21/56 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/544

CPC classification number: H01L21/565 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/823468 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a lower mold layer on a substrate that includes first and second regions, forming first and second intermediate mold patterns on the first and second regions, respectively, forming first spacers on sidewalls of the first and second intermediate mold patterns, etching the lower mold layer to form first and second lower mold patterns on the first and second regions, respectively, and etching the substrate to form active patterns and dummy patterns on the first and second regions, respectively. A first distance between a pair of the first intermediate mold patterns may be greater than a second distance between a pair of the second intermediate mold patterns, and the second lower mold patterns may include at least one first merged pattern, whose width is substantially equal to the second distance.

公开(公告)号：US20170271335A1

公开(公告)日：2017-09-21

申请号：US15615643

申请日：2017-06-06

Applicant: Samsung Electronics Co. Ltd.

Inventor： Junggil YANG ,  SANGSU KIM ,  TaeYong KWON ,  SUNG GI HUR

IPC: H01L27/092 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/42392

Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.

公开(公告)号：US20160372474A1

公开(公告)日：2016-12-22

申请号：US15249518

申请日：2016-08-29

Applicant: Samsung Electronics Co. Ltd.

Inventor： Junggil YANG ,  SANGSU KIM ,  TaeYong KWON ,  SUNG GI HUR

IPC: H01L27/092 ,  H01L21/306 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/42392

Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.

Abstract translation: 制造半导体器件的方法包括制备包括第一区域和第二区域的衬底，在第一和第二区域上依次形成第一半导体层和第二半导体层，图案化第一和第二半导体层以形成下部半导体 图案和上半导体图案，选择性地去除第二区域上的下半导体图案以形成间隙区域，以及分别在第一和第二区域形成栅电极。