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公开(公告)号：US20250107086A1
公开(公告)日：2025-03-27
申请号：US18737295
申请日：2024-06-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hanbyeol LEE , Younghwan SON , Sangdon LEE , Shinhwan KANG , Sukkang SUNG
Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other including upper gate electrodes, memory gate electrodes and lower gate electrodes sequentially stacked from the horizontal conductive layer; a horizontal connection portion between the memory gate electrodes and the lower gate electrodes; channel structures penetrating through the gate electrodes and extending in the first direction in the first region; isolation regions penetrating through the gate electrodes; an insulating region extending from a lowermost surface of the gate electrodes and penetrating through at least one of the lower gate electrodes between the isolation regions; wherein an upper surface of the insulating region has a first width, a lower surface has a second width greater than the first width, an upper surface of each of the channel structures has a third width, and a lower surface has a fourth width smaller than the third width.
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公开(公告)号：US20200350329A1
公开(公告)日：2020-11-05
申请号：US16690929
申请日：2019-11-21
Applicant: Samsung Electronics Co, Ltd.
Inventor： Kohji KANAMORI , Seogoo KANG , Shinhwan KANG
IPC: H01L27/11582 , H01L29/417
Abstract: A semiconductor memory device including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers, gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, and channel structures penetrating the first, second and third semiconductor layers and the gate electrodes, each respective channel structure of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film including a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, and the charge storage film including an upper cover protruding toward the outside of the respective channel structure.
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公开(公告)号：US20230009932A1
公开(公告)日：2023-01-12
申请号：US17838575
申请日：2022-06-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunyoung LEE , Shinhwan KANG , Seokcheon BAEK
IPC: H01L23/00 , H01L23/535 , H01L27/11556 , H01L27/11529 , H01L27/11582 , H01L27/11573
Abstract: A semiconductor device including a substrate including first, second, and third regions; a peripheral circuit structure on the substrate and including a peripheral circuit and wiring layers connected to the peripheral circuit; a common source plate on the peripheral circuit structure and extending in a horizontal direction; gate electrodes on the common source plate on the first and second regions, spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, the gate electrodes having a stair shape on the second region; a channel structure extending in the first direction through the gate electrodes on the first region; a first conductive through-via penetrating the common source plate on the third region and electrically connected to the wiring layers; and a dummy insulating pillar adjacent to the first conductive through-via on the third region and connected to an upper surface of the common source plate.
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公开(公告)号：US20210035987A1
公开(公告)日：2021-02-04
申请号：US16844234
申请日：2020-04-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Haemin LEE , Jongwon KIM , Shinhwan KANG , Kohji KANAMORI , Jeehoon HAN
IPC: H01L27/1157 , H01L27/11578 , H01L27/11521 , H01L27/11556
Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.
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公开(公告)号：US20240414922A1
公开(公告)日：2024-12-12
申请号：US18809829
申请日：2024-08-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kohji KANAMORI , Shinhwan KANG , Jeehoon HAN
Abstract: A semiconductor device includes a substrate; a stack structure on the substrate and including an alternating stack of interlayer insulating layers and gate electrodes; first and second separation regions each extending through the stack structure and extending in a first direction; a first upper separation region between the first and second separation regions and extending through a portion of the stack structure; a plurality of channel structures between the first and second separation regions and extending through the stack structure; and a plurality of first vertical structures each extending through a particular one of the first and second separation regions. Each of the first and second separation regions has a first width in a second direction that is perpendicular to the first direction. Each first vertical structure has a second width in the second direction, the second width being greater than the first width.
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Patent Agency Ranking
公开(公告)号：US20240015968A1
公开(公告)日：2024-01-11
申请号：US18370543
申请日：2023-09-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kohji KANAMORI , Shinhwan KANG
IPC: H10B43/27 , H01L23/522 , H01L23/528 , H01L21/02 , H01L21/311 , H01L21/28 , H10B43/10 , H10B43/40 , H10B43/50
CPC classification number: H10B43/27 , H01L23/5226 , H01L23/528 , H01L21/02667 , H01L21/31144 , H01L29/40117 , H01L21/31111 , H01L21/02532 , H01L21/02592 , H01L21/02636 , H01L21/31116 , H10B43/10 , H10B43/40 , H10B43/50
Abstract: A vertical memory device including gate electrodes on a substrate, the gate electrodes being spaced apart in a first direction and stacked in a staircase arrangement; a channel extending through the gate electrodes in the first direction; a first contact plug extending through a pad of a first gate electrode to contact an upper surface of the first gate electrode, the first contact plug extending through a portion of a second gate electrode, and the second gate electrode being adjacent to the first gate electrode; a first spacer between the first contact plug and sidewalls of the first gate electrode and the second gate electrode facing the first contact plug, the first spacer electrically insulating the first contact plug from the second gate electrode; and a first burying pattern contacting bottom surfaces of the first contact plug and the first spacer, the first burying pattern including an insulating material.
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公开(公告)号：US20210408040A1
公开(公告)日：2021-12-30
申请号：US17473006
申请日：2021-09-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhwan KANG , Younghwan SON , Haemin LEE , Kohji KANAMORI , Jeehoon HAN
IPC: H01L27/11582 , H01L27/11565 , H01L27/11519 , H01L27/11556
Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.
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公开(公告)号：US20220216234A1
公开(公告)日：2022-07-07
申请号：US17705513
申请日：2022-03-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kohji KANAMORI , Shinhwan KANG
IPC: H01L27/11582 , H01L23/522 , H01L23/528 , H01L27/11573 , H01L27/11575 , H01L27/11565 , H01L21/02 , H01L21/311 , H01L21/28
Abstract: A vertical memory device including gate electrodes on a substrate, the gate electrodes being spaced apart in a first direction and stacked in a staircase arrangement; a channel extending through the gate electrodes in the first direction; a first contact plug extending through a pad of a first gate electrode to contact an upper surface of the first gate electrode, the first contact plug extending through a portion of a second gate electrode, and the second gate electrode being adjacent to the first gate electrode; a first spacer between the first contact plug and sidewalls of the first gate electrode and the second gate electrode facing the first contact plug, the first spacer electrically insulating the first contact plug from the second gate electrode; and a first burying pattern contacting bottom surfaces of the first contact plug and the first spacer, the first burying pattern including an insulating material.
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公开(公告)号：US20220093631A1
公开(公告)日：2022-03-24
申请号：US17352862
申请日：2021-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kohji KANAMORI , Shinhwan KANG , Jeehoon HAN
IPC: H01L27/11575 , H01L27/11519 , H01L27/11556 , H01L27/11548 , H01L27/11529 , H01L27/11565 , H01L27/11582 , H01L27/11573
Abstract: A semiconductor device includes a substrate; a stack structure on the substrate and including an alternating stack of interlayer insulating layers and gate electrodes; first and second separation regions each extending through the stack structure and extending in a first direction; a first upper separation region between the first and second separation regions and extending through a portion of the stack structure; a plurality of channel structures between the first and second separation regions and extending through the stack structure; and a plurality of first vertical structures each extending through a particular one of the first and second separation regions. Each of the first and second separation regions has a first width in a second direction that is perpendicular to the first direction. Each first vertical structure has a second width in the second direction, the second width being greater than the first width.
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公开(公告)号：US20210375924A1
公开(公告)日：2021-12-02
申请号：US17400224
申请日：2021-08-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kohji KANAMORI , Seogoo KANG , Shinhwan KANG
IPC: H01L27/11582 , H01L29/417
Abstract: A semiconductor memory device including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers, gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, and channel structures penetrating the first, second and third semiconductor layers and the gate electrodes, each respective channel structure of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film including a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, and the charge storage film including an upper cover protruding toward the outside of the respective channel structure.
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