公开(公告)号：US20230170290A1

公开(公告)日：2023-06-01

申请号：US17886872

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： YUN-HEE LEE ,  JAESUN KIM ,  SEOKBEOM YONG ,  WONJAE LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/2919 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2924/0665

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate and a semiconductor chip on the redistribution substrate. The redistribution substrate includes a plurality of first conductive patterns including a pair of first signal patterns that are adjacent to each other, and a plurality of second conductive patterns on surfaces of the first conductive patterns and coupled to the first conductive patterns. The second conductive patterns include a ground pattern insulated from the pair of first signal patterns. The ground pattern has an opening that penetrates the ground pattern. When viewed in plan, the pair of first signal patterns overlap the opening.

公开(公告)号：US20250149458A1

公开(公告)日：2025-05-08

申请号：US18738439

申请日：2024-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyeong Park ,  SANG SUB SONG ,  SEOKBEOM YONG

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/16 ,  H10B80/00

Abstract: A semiconductor package comprises an interconnection structure including a plurality of signal wires and a plurality of ground wires, wherein the plurality of signal wires and the plurality of ground wires are alternately arranged in the first horizontal direction and extend in the second horizontal direction intersecting with the first horizontal direction; and a first semiconductor chip and a second semiconductor chip on the interconnection structure, wherein the interconnection structure includes first regions under the first semiconductor chip and under the second semiconductor chip and a second region between the first regions, and the plurality of signal wires connect the first semiconductor chip and the second semiconductor chip; wherein each of the plurality of signal wires has a first width in the first horizontal direction in the first region and a second width in the first horizontal direction in the second region, and the second width is greater than the first width.

公开(公告)号：US20240282750A1

公开(公告)日：2024-08-22

申请号：US18413184

申请日：2024-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEOKBEOM YONG ,  Kyungsuk Oh

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06568

Abstract: A semiconductor package including a package substrate; an upper chip on the package substrate; a passive element chip between the upper chip and the package substrate; and a lower chip between the passive element chip and the package substrate, wherein the passive element chip includes a through electrode connected to the lower chip; and a plurality of passive elements on the through electrode, and the upper surface of the passive element chip is in contact with the lower surface of the upper chip.

公开(公告)号：US20230130453A1

公开(公告)日：2023-04-27

申请号：US17827018

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEOKBEOM YONG ,  DONGCHUL YANG ,  YUNHEE LEE ,  SEUNGSOO HA

IPC: H01L23/498 ,  H01L25/10 ,  H01L25/18

Abstract: Provided is a semiconductor package with high reliability signal characteristics and a memory module including the semiconductor package. The semiconductor package includes a package substrate, a semiconductor chip mounted on the package substrate, and connection terminals arranged on a lower surface of the package substrate. The connection terminals are arranged in a two-dimensional array structure in a first direction and a second direction perpendicular to the first direction, and two adjacent terminals with a shortest distance therebetween among data signal (DQ) terminals and command and address signal (CA) terminals included in the connection terminals are arranged in a diagonal direction between the first direction and the second direction.