公开(公告)号：US10014407B2

公开(公告)日：2018-07-03

申请号：US15401176

申请日：2017-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Gu Kang ,  Myoungkyu Park ,  Chulho Chung

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/51 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7816 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/513 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes an active region defined by an isolation layer. A source region portion, a drain region portion and a channel region are located in the active region. The channel region includes a first portion located close to the source region portion and a second portion having a higher threshold voltage than the first portion.

公开(公告)号：US20230143543A1

公开(公告)日：2023-05-11

申请号：US17819936

申请日：2022-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongsun Kim ,  Shigenobu Maeda ,  Myoungkyu Park

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/6656 ,  H01L29/66545

Abstract: A semiconductor device includes an active fin protruding from a substrate, extending in a first direction, and defined by a device isolation layer. Gate structures intersect the active fin and extend in a second direction. Each of the gate structures includes a gate and gate spacers on side surfaces of the gate. Epitaxial layers are disposed on the active fin, on opposite sides of the gate structure, and include a first epitaxial layer providing a drain region and a second epitaxial layer providing a source region. The gate spacers include a first spacer disposed between the first epitaxial layer and the gate. The first spacer includes a first region extending in a third direction, along a side surface of the gate, and a second region extending from a lower portion of the first region in a direction away from the gate.

公开(公告)号：US20250151304A1

公开(公告)日：2025-05-08

申请号：US19009795

申请日：2025-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongsun Kim ,  Shigenobu Maeda ,  Myoungkyu Park

IPC: H10D30/01 ,  H10D30/62 ,  H10D84/01 ,  H10D84/03

Abstract: A method of manufacturing a semiconductor device includes forming an active fin protruding from a substrate and extending in a first direction; forming sacrificial gate patterns intersecting the active fin and extend in a second direction; forming recess regions by etching the active fin on at least one side of each of the sacrificial gate patterns; forming source/drain regions on the recess regions; removing the sacrificial gate patterns to form openings; and forming a gate dielectric layer and a gate electrode such that gate structures are formed to cover the active fin in the openings. The source/drain regions are formed by an epitaxial growth process and an in-situ doping process of doping first conductivity-type impurity elements. In at least one of the source/drain regions, after the in-situ doping process is performed, counter-doping is performed using second conductivity-type impurity elements different from the first conductivity-type impurity elements to decrease carrier concentration.

公开(公告)号：US12218223B2

公开(公告)日：2025-02-04

申请号：US17877251

申请日：2022-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongsun Kim ,  Shigenobu Maeda ,  Myoungkyu Park

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device includes forming an active fin protruding from a substrate and extending in a first direction; forming sacrificial gate patterns intersecting the active fin and extend in a second direction; forming recess regions by etching the active fin on at least one side of each of the sacrificial gate patterns; forming source/drain regions on the recess regions; removing the sacrificial gate patterns to form openings; and forming a gate dielectric layer and a gate electrode such that gate structures are formed to cover the active fin in the openings. The source/drain regions are formed by an epitaxial growth process and an in-situ doping process of doping first conductivity-type impurity elements. In at least one of the source/drain regions, after the in-situ doping process is performed, counter-doping is performed using second conductivity-type impurity elements different from the first conductivity-type impurity elements to decrease carrier concentration.