公开(公告)号：US20220103163A1

公开(公告)日：2022-03-31

申请号：US17175818

申请日：2021-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ankur GUPTA ,  Lava Kumar PULLURU ,  Parvinder Kumar RANA

IPC: H03K3/356 ,  H03K19/0185 ,  G11C11/412 ,  G11C11/419

Abstract: An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the A output of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.

公开(公告)号：US20240071438A1

公开(公告)日：2024-02-29

申请号：US18051142

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar PULLURU ,  Gopi Sunanth Kumar Gogineni ,  Manish Chandra Joshi ,  Pushp Khatter

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/109 ,  G11C7/12 ,  G11C7/22

Abstract: Various example embodiments of the inventive concepts include a SRAM apparatus including a left memory array and right memory array, each of the left memory array and the right memory array including a left memory array and a right memory array, each comprising a plurality of columns, the plurality of columns in each of the left memory array and the right memory array divided into a plurality of segments, and each of the segments comprising a plurality of memory bit cells, and central driver circuitry comprising a plurality of driver devices, each of the plurality of driver devices communicatively connected to a corresponding segment of the plurality of segments through a corresponding metal control line of a plurality of metal control lines, the central driver circuitry configured to route at least one array signal to at least one segment of the plurality of segments.

公开(公告)号：US20180174657A1

公开(公告)日：2018-06-21

申请号：US15665988

申请日：2017-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Parvinder Kumar RANA ,  Lava Kumar PULLURU ,  Manish Chandra JOSHI

IPC: G11C16/32 ,  G11C16/08

CPC classification number: G11C16/32 ,  G11C7/222 ,  G11C8/12 ,  G11C16/08

Abstract: A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.

公开(公告)号：US20240161821A1

公开(公告)日：2024-05-16

申请号：US18163584

申请日：2023-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Poornima VENKATASUBRAMANIAN ,  Pushp KHATTER ,  Lava Kumar PULLURU ,  Manish Chandra JOSHI ,  Ved PRAKASH ,  Anurag KUMAR ,  Surendra DESHMUKH

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.

公开(公告)号：US20230282251A1

公开(公告)日：2023-09-07

申请号：US17750690

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lava Kumar PULLURU ,  Poornima VENKATASUBRAMANIAN ,  Manish Chandra JOSHI ,  Ved PRAKASH ,  Pushp KHATTER

IPC: G11C7/10 ,  H03K3/037

CPC classification number: G11C7/1039 ,  G11C7/1066 ,  G11C7/1093 ,  H03K3/0372

Abstract: A memory device includes at least one bitcell; read circuitry coupled to the at least one bitcell; and screening circuitry coupled to the read circuitry, wherein the screening circuitry includes a master slave flip-flop configured to store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and a DOUT window controller coupled to the master slave flip-flop and configured to generate and control a master clock signal for the master latch to determine if the at least one bitcell is a weak bitcell; and generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal.

公开(公告)号：US20200075070A1

公开(公告)日：2020-03-05

申请号：US16166647

申请日：2018-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ankur GUPTA ,  Abhishek KESARWANI ,  Parvinder Kumar RANA ,  Manish Chandra JOSHI ,  Lava Kumar PULLURU

IPC: G11C8/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/08

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

公开(公告)号：US20190147943A1

公开(公告)日：2019-05-16

申请号：US16190278

申请日：2018-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Parvinder Kumar RANA ,  Lava Kumar PULLURU ,  Shuvadeep Kumar ,  Ankur GUPTA

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/222 ,  G11C8/08 ,  G11C8/18 ,  G11C11/418

Abstract: Embodiments herein provide a method for reducing power dissipation in a Static Random Access Memory (SRAM) device. The method includes determining, by the tracking circuit, whether at least one SRAM Bit-Cell discharges power from at least one BL exceeding a pre-defined voltage level required for a sense amplifier to perform a read operation. Furthermore, the method includes reducing, by the WL driver, the power discharged from the at least one BL by controlling a WL voltage power supply switch of the WL driver using a SAE signal and adjusting a pulse width of the at least one WL to pull down the at least one WL using a NMOS circuit when the at least one SRAM Bit-Cell discharges the power from the at least one BL exceeding the pre-defined voltage level.