公开(公告)号：US20250060967A1

公开(公告)日：2025-02-20

申请号：US18642977

申请日：2024-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghyun LEE ,  Jinin SO ,  Kyungsoo KIM ,  Sangsu PARK ,  Jin JUNG ,  Jeonghyeon CHO

IPC: G06F9/30 ,  G06F9/48 ,  G06F17/16

Abstract: Various example embodiments may include methods of operating a network device, non-transitory computer readable media including computer readable instructions for operating a network device, systems including a network device, and/or a compute express link (CXL) switching device for synchronizing data. A CXL-based system includes a plurality of CXL processing devices configured to perform matrix multiplication calculation based on input vector data and a partial matrix, and output at least one interrupt signal and at least one packet based on results of the matrix multiplication calculation, the at least one packet including output vector data and characteristic data associated with the output vector data, and a CXL switching device configured to, synchronize the output vector data, the synchronizing including performing a calculation operation on the output vector data based on the interrupt signal and the packet, and provide the synchronized vector data to the plurality of CXL processing devices.

公开(公告)号：US20230292508A1

公开(公告)日：2023-09-14

申请号：US17961035

申请日：2022-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyen-Hee LEE ,  Kyungsoo KIM

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/41733 ,  H01L29/42392

Abstract: A three dimensional semiconductor device includes first, second, third and fourth source/drain patterns sequentially stacked on a substrate, a contact structure on the first to fourth source/drain patterns and a contact line on the contact structure. The contact structure includes a first active contact on the first source/drain pattern, a second active contact on the second source/drain pattern, a third active contact on the third source/drain pattern, and a fourth active contact on the fourth source/drain pattern. A first vertical extension part of the first active contact is adjacent to one side of the contact structure, and a second vertical extension part of the second active contact is adjacent to the other side of the contact structure. A third vertical extension part of the third active contact is disposed between the first and second vertical extension parts and is closer to the first vertical extension part.

公开(公告)号：US20220267939A1

公开(公告)日：2022-08-25

申请号：US17743051

申请日：2022-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahhyun KIM ,  Jikyoung KIM ,  Kyoungae LIM ,  Jimin HONG ,  Kyungsoo KIM ,  Heejung KIM

IPC: D06F34/05 ,  D06F34/32 ,  D06F34/06 ,  H04W4/02 ,  G06Q30/06

Abstract: An electronic device is provided. The electronic apparatus includes a memory in which an application is stored, a display, a position sensor, and a processor which executes the application to acquire user position information corresponding to a user terminal position sensed by the position sensor, and control a display to provide a user interface (UI) for controlling a cycle time of a washing apparatus, the UI being provided on the basis of information related to the cycle time of the washing apparatus and the user position information.

公开(公告)号：US20210349730A1

公开(公告)日：2021-11-11

申请号：US17115924

申请日：2020-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonggeon LEE ,  Kyungsoo KIM ,  Jinin SO ,  Yongsuk KWON ,  Jin JUNG ,  Jeonghyeon CHO

IPC: G06F9/4401 ,  G06N20/00

Abstract: A booting method of a computing system, which includes a memory module including a processing device connected to a plurality of memory devices, including: powering up the computing system; after powering up the computing system, performing first memory training on the plurality of memory devices by the processing device in the memory module, and generating a module ready signal indicating completion of the first memory training; after powering up the computing system, performing a first booting sequence by a host device, the host device executing basic input/output system (BIOS) code of a BIOS memory included in the computing system; waiting for the module ready signal to be received from the memory module in the host device after performing the first booting sequence; and receiving the module ready signal in the host device, and performing a second booting sequence based on the module ready signal.

公开(公告)号：US20240063018A1

公开(公告)日：2024-02-22

申请号：US18366470

申请日：2023-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seowoo NAM ,  Kyungsoo KIM

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877

Abstract: A method of fabricating a semiconductor device, includes forming a dielectric layer on a substrate; forming a hard mask layer on the dielectric layer; forming mandrel lines on the hard mask layer, each of the mandrel lines extending in a first direction; forming spacers on both sidewalls of each of mandrel lines; removing the plurality of mandrel lines from the spacers; forming a first linear opening corresponding to a first region of a space between adjacent ones of the spacers, in the hard mask layer; forming a second linear opening corresponding to a second region of the space between the adjacent ones, the second linear opening being adjacent to the first linear opening in the first direction; forming trenches in the dielectric layer using the hard mask layer; and interconnection lines by filling the trenches with a conductive material.

公开(公告)号：US20220399331A1

公开(公告)日：2022-12-15

申请号：US17561867

申请日：2021-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhee KIM ,  Kyungsoo KIM ,  Dongil BAE ,  Sungman WHANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor integrated circuit device including a substrate with a first element region of a P type and a second element region of an N type, a channel active region that extends in the first element region or the second element region, the channel active region including a plurality of channels, a plurality of gate lines that extend in a second direction intersecting and include a gate metal layer, and a gate insulating film in contact with the gate metal layer, a plurality of first spacers on opposite side portions of respective ones of the gate lines, and a plurality of source/drain regions that are between ones of the plurality of gate lines. The channel active region includes a first channel directly on the substrate, and a second channel spaced apart from the first channel and extends into the gate metal layer.

公开(公告)号：US20240211424A1

公开(公告)日：2024-06-27

申请号：US18448701

申请日：2023-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungsoo KIM ,  Jinin SO ,  Yongsuk KWON ,  Jin JUNG

IPC: G06F13/40 ,  G06F11/07 ,  G11C5/14

CPC classification number: G06F13/4022 ,  G06F11/0772 ,  G06F13/4068 ,  G11C5/148

Abstract: A memory expander includes memory sub-modules, power management integrated circuits, a controller, and a power controller. The memory sub-modules store data, and each of the memory sub-modules includes one or more memories. The power management integrated circuits independently supply powers to the memory sub-modules, respectively. The controller communicates with an external device through an interface (e.g., compute express link (CXL)), controls operations of the memory sub-modules, and checks whether the memory sub-modules are abnormal. The power controller controls operations of the power management integrated circuits. In response to a first memory sub-module becoming abnormal, the power controller controls a first power management integrated circuit to block a first power supplied to the first memory sub-module.

公开(公告)号：US20230280646A1

公开(公告)日：2023-09-07

申请号：US17972231

申请日：2022-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo KIM ,  Sooryong LEE ,  Jaewon YANG ,  Sangchul YEO ,  Hyeok LEE

IPC: G03F1/36 ,  G03F1/80 ,  G03F7/20

CPC classification number: G03F1/36 ,  G03F1/80 ,  G03F7/705

Abstract: The inventive concept provides a corner rounding method of a deep learning-based optical proximity correction (OPC) pattern by which patterning reliability may be ensured, and an OPC method and a mask manufacturing including the corner rounding method. The corner rounding method of a deep learning-based OPC pattern includes: obtaining a contour of a photoresist (PR) pattern or an etching pattern on a wafer; obtaining a square layout of the PR pattern or the etching pattern corresponding to the contour; generating a transform model through deep learning with the square layout and the contour; and obtaining a rounded layout target with respect to a square layout target by using the transform model.

公开(公告)号：US20230223323A1

公开(公告)日：2023-07-13

申请号：US17979480

申请日：2022-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungsoo KIM ,  Kyenhee LEE

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/538 ,  H01L25/07 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/481 ,  H01L23/49844 ,  H01L23/5384 ,  H01L25/07 ,  H01L24/16 ,  H01L24/05 ,  H01L2224/16146 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2924/15311

Abstract: A semiconductor package is provided. The semiconductor package includes: a first semiconductor chip including a first bonding structure; , a first front-end level layer including a first integrated circuit device; a first sub-back-end level layer including a plurality of first metal wire layers, an input and output device level layer including a two-dimensional input and output device, and a second sub-back-end level layer including a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device. The semiconductor package also includes a second semiconductor chip including a bonding structure that is bonded to the first bonding structure; a second front-end level layer including a second integrated circuit device, and a second back-end level layer including a plurality of third metal wire layers electrically connected to the second integrated circuit device.

公开(公告)号：US20220206968A1

公开(公告)日：2022-06-30

申请号：US17383056

申请日：2021-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyeon CHO ,  Yongsuk KWON ,  Kyungsoo KIM ,  Jonghoon KIM ,  Jonghyun SEOK ,  Jonggeon LEE

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/10 ,  G11C5/06

Abstract: A memory module includes a memory substrate including a main connector and an auxiliary connector, configured to be connected to an external device; and a plurality of memory chips mounted on at least one of a first surface or a second surface of the memory substrate, wherein the main connector is disposed on one side of the memory substrate, and the auxiliary connector is disposed on the second surface of the memory substrate.